View RX210-15_8210383.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

datasheet r01ds0041ej0150 rev.1.50 page 1 of 221 oct 18, 2013 rx210 group renesas mcus features 32-bit rx cpu core ? max. operating frequency: 50 mhz capable of 78 dmips in operation at 50 mhz ? accumulator handles 64-bit result s (for a single instruction) from 32- 32-bit operations ? multiplication and division unit handles 32- 32-bit operations (multiplication inst ructions take one cpu clock cycle) ? fast interrupt ? cisc harvard architecture with 5-stage pipeline ? variable-length instructions, ultra-compact code ? on-chip debugging circuit low power design and architecture ? operation from a single 1.62-v to 5.5-v supply ? 1.62-v operation available (at up to 20 mhz) ? deep software standby mode with rtc remaining usable ? four low power consumption modes on-chip flash memory for code, no wait states ? 50-mhz operation, 20-ns read cycle ? no wait states for r eading at full cpu speed ? 64-k to 1-mbyte capacities ? user code programmable via the sci ? programmable at 1.62 v ? for instructions and operands on-chip data flash memory ? 8 kbytes (number of times of reprogramming: 100,000) ? erasing and programming impose no load on the cpu. on-chip sram, no wait states ? 12-k to 96-kbyte size capacities dma ? dmac: incorporates four channels ? dtc: four transfer modes elc ? module operation can be initiated by event signals without going through interrupts. ? modules can operate while the cpu is sleeping. reset and supply management ? nine types of reset, including the power-on reset (por) ? low voltage detection (lvd) with voltage settings clock functions ? frequency of external clock: up to 20 mhz ? frequency of the oscillator for sub-clock generation: 32.768 khz ? pll circuit input: 4 mhz to 12.5 mhz ? on-chip low- and high-speed os cillators, dedicated on-chip low-speed oscillator for the iwdt ? generation of a dedicated 32.768-khz clock for the rtc ? clock frequency accuracy measurement circuit (cac) realtime clock ? adjustment functions (30 se conds, leap year, and error) ? year and month display or 32-bit second display (binary counter) is selectable ? time capture function ? time capture on event-signal i nput through external pins ? rtc capable of initiating retu rn from deep software standby mode independent watchdog timer ? 125-khz on-chip oscillator produ ces a dedicated clock signal to drive iwdt operation. useful functions for iec60730 compliance ? self-diagnostic and disconn ection-detection assistance functions for the a/d converter, clock frequency accuracy measurement circuit, independent watchdog timer, functions to assist in ram testing, etc. up to 15 communications channels ? sci with many useful functions (up to 13 channels) asynchronous mode, clock s ynchronous mode, smart card interface ? i 2 c bus interface: transfer at up to 400 kbps, capable of smbus operation (one channel) ? rspi (one channel): transfer at up to 16 mbps (768-kbyte/ 1-mbyte flash memory or 144/145-pin products) external address space ? four cs areas (4 16 mbytes) ? 8- or 16-bit bus space is selectable per area up to 20 extend ed-function timers ? 16-bit mtu: input capture, output compare, complementary pwm output, phase counting mode (six channels) ? 16-bit tpu: input capture, out put capture, phase counting mode (six channels) ? 8-bit tmr (four channels) ? 16-bit compare-match timers (four channels) 12-bit a/d converter ? capable of conversion within 1 s ? sample-and-hold circuits (for three channels) ? three-channel synchronized sampling available ? self-diagnostic function a nd analog input disconnection detection assistance function 10-bit d/a converter analog comparator general i/o ports ? 5-v tolerant, open drain, inpu t pull-up, switching of driving ability mpc ? multiple locations are selectab le for i/o pins of peripheral functions temperature sensor operating temp. range ?? 40? c to +85 ? c ?? 40? c to +105 ? c applications ? 69wlbga (swbg0069la-a): general consumer equipment ? other than above package: general industrial and consumer equipment plqp0144ka-a 20 20 mm, 0.5-mm pitch plqp0100kb-a 14 14 mm, 0.5-mm pitch plqp0080kb-a 12 12 mm, 0.5-mm pitch plqp0064kb-a 10 10 mm, 0.5-mm pitch plqp0048kb-a 7 7 mm, 0.5-mm pitch plqp0080ja-a 14 14 mm, 0.65-mm pitch plqp0064ga-a 14 14 mm, 0.8-mm pitch ptlg0145ka-a 7 7 mm, 0.5-mm pitch ptlg0100ja-a 7 7 mm, 0.65-mm pitch ptlg0100ka-a 5.5 5.5 mm, 0.5-mm pitch ptlg0064ja-a 6 6 mm, 0.65-mm pitch swbg0069la-a 3.91 4.26mm, 0.40-mm pitch 50-mhz 32-bit rx mcus, 78 dmi ps, up to 1-mb flash memory, 12-bit a/d, 10-bit d/a, elc, mpc, rtc, up to 15 comms channels; incorporating functions for iec60730 compliance r01ds0041ej0150 rev.1.50 oct 18, 2013
r01ds0041ej0150 rev.1.50 page 2 of 221 oct 18, 2013 rx210 group 1. overview 1.overview 1.1 outline of specifications table 1.1 lists the specifications in outline, and table 1.2 gives a comparison of the functions of products in different packages. table 1.1 is for products with the greatest number of functions , so numbers of peripheral modules and channels will differ in accord with the package. for details, see table 1.2, comparison of func tions for different packages . this product includes chip version a (part no.: r5f5210xa xxx), chip version b (part no.: r5f5210xbxxx), and chip version c (part no: r5f5210xcxxx). for the specification differences between chip versions a, b, and c, see table 1, specification differences depending on chip versions . table 1.1 outline of specifications (1 / 5) classification module/function description cpu cpu ? maximum operating frequency: 50 mhz ? 32-bit rx cpu ? minimum instruction exec ution time: one instruction per st ate (cycle of the system clock) ? address space: 4-gbyte linear ? register general purpose: sixteen 32-bit registers control: eight 32-bit registers accumulator: one 64-bit register ? basic instructions: 73 ? dsp instructions: 9 ? addressing modes: 10 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32 ? 32 ? 64 bits ? on-chip divider: 32 / 32 ? 32 bits ? barrel shifter: 32 bits memory rom ? capacity: 64 k/96 k/128 k/256 k/384 k/512 k/768 kbytes/1 mbyte ? 50 mhz, no-wait memory access ? on-board programming: 3 types off-board programming ram ? capacity: 12 k/16 k/20 k/32 k/64 k/96 kbytes ? 50 mhz, no-wait memory access e2 dataflash ? capacity: 8 kbytes ? number of times for programming/erasing: 100,000 mcu operating mode single-chip mode, on-chip rom enabled expansion mode, and on-chip rom disabled expansion mode (software switching) clock clock generation circuit ? main clock oscillator, sub-clock oscillator, low-s peed on-chip oscillator, high-speed on-chip oscillator, pll frequency synthesizer, and iwdt-dedicated on-chip oscillator ? oscillation stop detection ? measuring circuit for accuracy of clo ck frequency (clock-accuracy check: cac) ? independent settings for the system clock (iclk), peripheral module clock (pclk), external bus clock (bclk), and flashif clock (fclk) the cpu and system sections such as other bus masters run in synchronization with the system clock (iclk): 50 mhz (at max.) peripheral modules run in synchronization with the peripheral module clock (pclk): 32 mhz (at max.) devices connected to the external bus run in synch ronization with the external bus clock (bclk): 12.5 mhz (at max.) the flash peripheral circuit runs in synchronizati on with the flashif clock (fclk): 32 mhz (at max.) reset res# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog timer reset, deep software standby reset, and software reset voltage detection voltage detection circuit (lvdaa) ? when the voltage on vcc falls below the voltage detection level, an internal reset or internal interrupt is generated. voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels
r01ds0041ej0150 rev.1.50 page 3 of 221 oct 18, 2013 rx210 group 1. overview low power consumption low power consumption facilities ? module stop function ? four low power consumption modes sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode function for lower operating power consumption ? operating power control modes [chip versions a and c] high-speed operating mode, middle-speed operating mode 1a, middle-speed operating mode 1b, low-speed operating mode 1, low-speed operating mode 2 [chip version b] high-speed operating mode, middle-speed operating mode 1a, middle-speed operating mode 1b, middle-speed operating mode 2a, middle-speed operating mode 2b, low-speed operating mode 1, low-speed operating mode 2 interrupt interrupt controller (icub) ? interrupt vectors: 167 ? external interrupts: 9 (nmi, irq0 to irq7 pins) ? non-maskable interrupts: 6 (the nmi pin, oscillation stop detection interrupt, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, wdt interrupt, and iwdt interrupt) ? 16 levels specifiable for the order of priority external bus extension ? the external address space can be divided into four areas (cs0 to cs3), each with independent control of access settings. capacity of each area: 16 mbytes (cs0 to cs3) a chip-select signal (cs0# to cs3#) can be output for each area. each area is specifiable as an 8-bit or 16-bit bus space the data arrangement in each area is selectable as little or big endian (only for data). bus format: separate bus, multiplex bus ? wait control ? write buffer facility dma dma controller (dmaca) ? 4 channels ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: software trigger, external in terrupts, and interrupt requests from peripheral functions data transfer controller (dtca) ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: interrupts ? chain transfer function i/o ports general i/o ports 145-pin/144-pin/100-pin/80-pin/69-pin/64-pin/48-pin ? i/o: 122/122/84/64/48/48/34 ? input: 1/1/1/1/1/1/1 ? pull-up resistors: 122/122/84/64/48/48/34 ? open-drain outputs: 76/76/54/44/35/35/26 ? 5-v tolerance:4/4/4/4/2/2* 1 /2 event link controller (elc) ? event signals of 59 types can be directly connected to the module ? operations of timer modules are selectable at event input ? capable of event link operation for ports b and e multi-function pin controller (mpc) ? capable of selecting input/output function from multiple pins table 1.1 outline of specifications (2 / 5) classification module/function description
r01ds0041ej0150 rev.1.50 page 4 of 221 oct 18, 2013 rx210 group 1. overview timers 16-bit timer pulse unit (tpua) ? (16 bits 6 channels) 1 unit ? maximum of 16 pulse-input/output possible ? select from among seven or eight coun ter-input clock signals for each channel ? supports the input capture/output compare function ? output of pwm waveforms in up to 15 phases in pwm mode ? support for buffered operation, phase-counting mode (two-phase encoder input) and cascade- connected operation (32 bits 2 channels) depending on the channel. ? capable of generating conversion start triggers for the a/d converters ? signals from the input capture pins are input via a digital filter ? clock frequency measuring method (products with 144 or more pins incorporate a tpu.) multi-function timer pulse unit 2 (mtu2a) ? (16 bits ? 6 channels) ? 1 unit ? up to 16 pulse-input/output lines and three pulse-input lines are available with six 16-bit timer channels ? select from among eight or seven counter-input clock signals for each channel (pclk/1, pclk/4, pclk/16, pclk/64, pclk/256, pclk/1024, mt clka, mtclkb, mtclkc, mtclkd) other than channel 5, for which only four signals are available. ? input capture function ? 21 output compare/input capture registers ? pulse output mode ? complementary pwm output mode ? reset synchronous pwm mode ? phase-counting mode ? generation of triggers for a/d converter conversion port output enable 2 (poe2a) controls the high-impedance state of the mtu?s waveform output pins 8-bit timer (tmr) ? (8 bits ? 2 channels) ? 2 units ? select from among seven internal clock signals (pclk1, pclk/2, pclk/8, pclk/32, pclk/64, pclk/1024, pclk/8192) and one external clock signal ? capable of output of pulse trains wi th desired duty cycles or of pwm signals ? the 2 channels of each unit can be cascaded to create a 16-bit timer ? capable of generating baud-rate clocks for sci5, sci6, and sci12 compare match timer (cmt) ? (16 bits ? 2 channels) ? 2 units ? select from among four clock signals (pclk/8, pclk/32, pclk/128, pclk/512) watchdog timer (wdta) ? 14 bits ? 1 channel ? select from among six counter-input clock signals (pclk/4, pclk/64, pclk/128, pclk/512, pclk/2048, pclk/8192) independent watchdog timer (iwdta) ? 14 bits ? 1 channel ? counter-input clock: iwdt-dedicated on-chip oscillator frequ ency d i vided by 1, 16, 32, 64, 128, or 256 realtime clock (rtcb) ? clock source: sub-clock ? time/calendar ? interrupt sources: alarm interrupt, periodic interrupt, and carry interrupt ? time-capture facility for three values table 1.1 outline of specifications (3 / 5) classification module/function description
r01ds0041ej0150 rev.1.50 page 5 of 221 oct 18, 2013 rx210 group 1. overview communication functions serial communications interfaces (scic, scid) ? 13 channels (channel 0 to 11: scic, channel 12: scid) ? serial communications modes: asynchronous, clock synchronous, and smart-card interface ? on-chip baud rate generator allows selection of the desired bit rate ? choice of lsb-first or msb-first transfer ? average transfer rate clock can be input fr om tmr timers (sci5, sci6, and sci12) ? simple iic ? simple spi ? master/slave mode supported (scid only) ? start frame and information frame are included (scid only) i 2 c bus interface (riic) ? 1 channel ? communications formats: i 2 c bus format/smbus format ? master/slave selectable ? supports the fast mode serial peripheral interface (rspi) ? 1 channel ? transfer facility using the mosi (master out, slave in), miso (mast er in, slave out), ssl (slave select), and rspi clock (rspck) signals enables serial transfer through spi operation (four lines) or clock- synchronous operation (three lines) ? capable of handling serial transfer as a master or slave ? data formats ? choice of lsb-first or msb-first transfer the number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or receiv ed in a single transfer operation (with each frame having up to 32 bits) ? double buffers for both transmission and reception 12-bit a/d converter (s12adb) ? 12 bits (16 channels ? 1 unit) ? 12-bit resolution ? minimum conversion time: 1.0 ? s per channel (in operation with adclk at 50 mhz) ? operating modes scan mode (single scan mode, continuous scan mode, and group scan mode) ? sample-and-hold function ? self-diagnosis for the a/d converter ? assistance in detecting disconnected analog inputs ? double-trigger mode (duplication of a/d conversion data) ? a/d conversion start conditions a software trigger, a trigger from a timer (mtu), an external trigger signal, or elc temperature sensor (tempsa) ? outputs the voltage that changes depending on the temperature ? pga gain switchable: four levels according to the voltage range d/a converter (da) ? 2 channels ? 10-bit resolution ? output voltage: 0 v to vrefh crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1 ? generation of crc codes for use with lsb-firs t or msb-first communications is selectable. comparator a (cmpa) ? 2 channels ? comparison of reference voltage and analog input voltage comparator b (cmpb) ? 2 channels ? comparison of reference voltage and analog input voltage data operation circuit (doc) comparison, addition, and subtraction of 16-bit data power supply voltage/operating frequency vcc = 1.62 to 1.8 v: 20 mhz, vcc = 1.8 to 2.7 v: 32 mhz, vcc = 2.7 to 5.5 v: 50 mhz operating temperature d version: ? 40 to +85 ? c, g version: ? 40 to +105 ? c* 2 table 1.1 outline of specifications (4 / 5) classification module/function description
r01ds0041ej0150 rev.1.50 page 6 of 221 oct 18, 2013 rx210 group 1. overview note 1. in chip version a of the part numbers below, port p17 is not 5 v tolerant. therefore there is only one port in these pro ducts. r5f52108adfm, r5f52107adfm, r5f52106adfm, and r5f52105adfm note 2. please contact renesas electronics sales office for derat ing of operation under ta = +85c to +105c. derating is the systematic reduction of load for th e sake of improved reliability. packages chip version a 100-pin tflga (ptlg0100ja-a) 7 7 mm, 0.65-mm pitch 100-pin lqfp (plqp0100kb-a) 14 14 mm, 0.5-mm pitch 80-pin lqfp (plqp0080kb-a) 12 12 mm, 0.5-mm pitch 64-pin lqfp (plqp0064kb-a) 10 10 mm, 0.5-mm pitch chip version b 145-pin tflga (ptlg0145ka-a) 7 7 mm, 0.5-mm pitch 100-pin tflga (ptlg0100ja-a) 7 7 mm, 0.65-mm pitch 100-pin tflga (ptlg0100ka-a) 5.5 5.5 mm, 0.5-mm pitch 64-pin tflga (ptlg0064ja-a) 6 6 mm, 0.65-mm pitch 144-pin lqfp (plqp0144ka-a) 20 20 mm, 0.5-mm pitch 100-pin lqfp (plqp0100kb-a) 14 14 mm, 0.5-mm pitch 80-pin lqfp (plqp0080kb-a) 12 12 mm, 0.5-mm pitch 80-pin lqfp (plqp0080ja-a) 14 14 mm, 0.65-mm pitch 64-pin lqfp (plqp0064kb-a) 10 10 mm, 0.5-mm pitch 64-pin lqfp (plqp0064ga-a) 14 14 mm, 0.8-mm pitch 48-pin lqfp (plqp0048kb-a) 7 7 mm, 0.5-mm pitch 69-pin wlbga (swbg0069la-a) 3.91 4.26mm, 0.40-mm pitch chip version c 100-pin tflga (ptlg0100ja-a) 7 7 mm, 0.65-mm pitch 100-pin lqfp (plqp0100kb-a) 14 14 mm, 0.5-mm pitch 80-pin lqfp (plqp0080kb-a) 12 12 mm, 0.5-mm pitch 80-pin lqfp (plqp0080ja-a) 14 14 mm, 0.65-mm pitch 64-pin lqfp (plqp0064kb-a) 10 10 mm, 0.5-mm pitch 64-pin lqfp (plqp0064ga-a) 14 14 mm, 0.8-mm pitch on-chip debugging system e1 emulator (fine interface) table 1.1 outline of specifications (5 / 5) classification module/function description
r01ds0041ej0150 rev.1.50 page 7 of 221 oct 18, 2013 rx210 group 1. overview table 1.2 comparison of functions for different packages module/functions rx210 group 144, 145 pins 100 pins 80 pins 64, 69 pins 48 pins external bus external bus width 16 bits not supported interrupt external interrupts nmi, irq0 to irq7 nmi, irq0 to irq2, irq4 to irq7 nmi, irq0, irq1, irq4 to irq7 dma dma controller 4 channels (dmac0 to dmac3) data transfer controller supported timers 16-bit timer pulse unit 6 channels (tpu0 to tpu5) not supported multi-function timer pulse unit 2 6 channels (mtu0 to mtu5) port output enable 2 poe0# to poe3#, poe8# 8-bit timer 2 channels 2 units compare match timer 2 channels 2 units realtime clock supported not supported watchdog timer supported independent watchdog timer supported communication functions serial communications interface (scic) 12 channels (sci0 to 11) 6 channels (sci0, 1, 5, 6, 8, 9) 5 channels (sci1, 5, 6, 8, 9) 4 channels (sci1, 5, 6, 8) serial communications interface (scid) 1 channel (sci12) i 2 c bus interface 1 channel serial peripheral interface 1 channel 12-bit a/d converter 16 channels (an000 to an015) 14 channels (an000 to an013) 12 channels (an000 to an004, an006, an008 to an013) 8 channels (an000 to an002, an006, an009 to an012) temperature sensor supported d/a converter 2 channels not supported crc calculator supported event link controller supported comparator a 2 channels comparator b 2 channels packages 145-pin tflga 144-pin lqfp 100-pin tflga 100-pin lqfp 80-pin lqfp 69-pin wlbga 64-pin tflga 64-pin lqfp 48-pin lqfp
r01ds0041ej0150 rev.1.50 page 8 of 221 oct 18, 2013 rx210 group 1. overview 1.2 list of products table 1.3 to table 1.7 are a list of products, and figure 1.1 shows how to read the pro duct part no., memory capacity, and package type. note: ? orderable part numbers are current as of when this manual was published. please make sure to refer to the relevant product page on the renesas website for the latest part numbers. table 1.3 list of products chip version a: d version (ta = ? 40 to +85c) group part no. orderable part no. package rom capacity ram capacity e2 dataflash operating frequency (max.) operating temperature rx210 r5f52108adfp r5f52108adfp#v0 plqp0100kb-a 512 kbytes 64 kbytes 8 kbytes 50 mhz ? 40 to +85c r5f52108adfn r5f52108adfn#v0 plqp0080kb-a r5f52108adfm r5f52108adfm#v0 plqp0064kb-a r5f52108adlj r5f52108adlj#u0 ptlg0100ja-a r5f52107adfp r5f52107adfp#v0 plqp0100kb-a 384 kbytes r5f52107adfn r5f52107adfn#v0 plqp0080kb-a r5f52107adfm r5f52107adfm#v0 plqp0064kb-a r5f52107adlj r5f52107adlj#u0 ptlg0100ja-a r5f52106adfp r5f52106adfp#v0 plqp0100kb-a 256 kbytes 32 kbytes r5f52106adfn r5f52106adfn#v0 plqp0080kb-a r5f52106adfm r5f52106adfm#v0 plqp0064kb-a r5f52106adlj r5f52106adlj#u0 ptlg0100ja-a r5f52105adfp r5f52105adfp#v0 plqp0100kb-a 128 kbytes 20 kbytes r5f52105adfn r5f52105adfn#v0 plqp0080kb-a r5f52105adfm r5f52105adfm#v0 plqp0064kb-a r5f52105adlj r5f52105adlj#u0 ptlg0100ja-a
r01ds0041ej0150 rev.1.50 page 9 of 221 oct 18, 2013 rx210 group 1. overview note: ? orderable part numbers are current as of when this manual was published. please make sure to refer to the relevant product page on the renesas website for the latest part numbers. note 1. these products are available for general consumer equipment only. table 1.4 list of products chip version b: d version (ta = ? 40 to +85c) group part no. orderable part no. package rom capacity ram capacity e2 dataflash operating frequency (max.) operating temperature rx210 r5f5210bbdfb r5f5210bbdfb#30 plqp0144ka-a 1 mbytes 96 kbytes 8 kbytes 50 mhz ? 40 to +85c r5f5210bbdlk r5f5210bbdlk#u0 ptlg0145ka-a r5f5210bbdfp r5f5210bbdfp#30 plqp0100kb-a r5f5210bbdlj r5f5210bbdlj#u0 ptlg0100ja-a r5f5210abdfb r5f5210abdfb#30 plqp0144ka-a 768 kbytes r5f5210abdlk r5f5210abdlk#u0 ptlg0145ka-a r5f5210abdfp r5f5210abdfp#30 plqp0100kb-a r5f5210abdlj r5f5210abdlj#u0 ptlg0100ja-a r5f52108bdfb r5f52108bdfb#30 plqp0144ka-a 512 kbytes 64 kbytes r5f52108bdlk r5f52108bdlk#u0 ptlg0145ka-a r5f52107bdfb r5f52107bdfb#30 plqp0144ka-a 384 kbytes r5f52107bdlk r5f52107bdlk#u0 ptlg0145ka-a r5f52106bdfb r5f52106bdfb#30 plqp0144ka-a 256 kbytes 32 kbytes r5f52106bdlk r5f52106bdlk#u0 ptlg0145ka-a r5f52106bdfp r5f52106bdfp#30 plqp0100kb-a r5f52106bdfn r5f52106bdfn#30 plqp0080kb-a r5f52106bdfm r5f52106bdfm#30 plqp0064kb-a r5f52106bdfl r5f52106bdfl#30 plqp0048kb-a r5f52106bdlj r5f52106bdlj#u0 ptlg0100ja-a r5f52106bdla r5f52106bdla#u0 ptlg0100ka-a r5f52106bdff r5f52106bdff#v0 plqp0080ja-a r5f52106bdfk r5f52106bdfk#30 plqp0064ga-a r5f52106bdlh r5f52106bdlh#u0 ptlg0064ja-a r5f52106bdbm * 1 r5f52106bdbm#w0 * 1 swbg0069la-a r5f52105bdfb r5f52105bdfb#30 plqp0144ka-a 128 kbytes 20 kbytes r5f52105bdlk r5f52105bdlk#u0 ptlg0145ka-a r5f52105bdfp r5f52105bdfp#30 plqp0100kb-a r5f52105bdfn r5f52105bdfn#30 plqp0080kb-a r5f52105bdfm r5f52105bdfm#30 plqp0064kb-a r5f52105bdfl r5f52105bdfl#30 plqp0048kb-a r5f52105bdlj r5f52105bdlj#u0 ptlg0100ja-a r5f52105bdla r5f52105bdla#u0 ptlg0100ka-a r5f52105bdff r5f52105bdff#v0 plqp0080ja-a r5f52105bdfk r5f52105bdfk#30 plqp0064ga-a r5f52105bdlh r5f52105bdlh#u0 ptlg0064ja-a r5f52105bdbm * 1 r5f52105bdbm#w0 * 1 swbg0069la-a r5f52104bdfm r5f52104bdfm#30 plqp0064kb-a 96 kbytes 16 kbytes r5f52104bdfl r5f52104bdfl#30 plqp0048kb-a r5f52104bdff r5f52104bdff#v0 plqp0080ja-a r5f52104bdlh r5f52104bdlh#u0 ptlg0064ja-a r5f52103bdfm r5f52103bdfm#30 plqp0064kb-a 64 kbytes 12 kbytes r5f52103bdfl r5f52103bdfl#30 plqp0048kb-a r5f52103bdff r5f52103bdff#v0 plqp0080ja-a r5f52103bdlh r5f52103bdlh#u0 ptlg0064ja-a
r01ds0041ej0150 rev.1.50 page 10 of 221 oct 18, 2013 rx210 group 1. overview note: ? please contact renesas electronics sales office for derat ing of operation under ta = +85c to +105c. derating is the systematic reduction of load for t he sake of improved reliability. note: ? orderable part numbers are current as of when this manual was published. please make sure to refer to the relevant product page on the renesas website for the latest part numbers. table 1.5 list of products chip version b: g version (ta = ? 40 to +105c) group part no. orderable part no. package rom capacity ram capacity e2 dataflash operating frequency (max.) operating temperature rx210 r5f5210bbgfb r5f5210bbgfb#30 plqp0144ka-a 1 mbytes 96 kbytes 8 kbytes 50 mhz ? 40 to +105c r5f5210bbgfp r5f5210bbgfp#30 plqp0100kb-a r5f5210abgfb r5f5210abgfb#30 plqp0144ka-a 768 kbytes r5f5210abgfp r5f5210abgfp#30 plqp0100kb-a r5f52108bgfb r5f52108bgfb#30 plqp0144ka-a 512 kbytes 64 kbytes r5f52107bgfb r5f52107bgfb#30 plqp0144ka-a 384 kbytes r5f52106bgfb r5f52106bgfb#30 plqp0144ka-a 256 kbytes 32 kbytes r5f52106bgfp r5f52106bgfp#30 plqp0100kb-a r5f52106bgfn r5f52106bgfn#30 plqp0080kb-a r5f52106bgfm r5f52106bgfm#30 plqp0064kb-a r5f52106bgfl r5f52106bgfl#30 plqp0048kb-a r5f52106bgff r5f52106bgff#v0 ptlg0100ja-a r5f52106bgfk r5f52106bgfk#30 plqp0064ga-a r5f52105bgfb r5f52105bgfb#30 plqp0144ka-a 128 kbytes 20 kbytes r5f52105bgfp r5f52105bgfp#30 plqp0100kb-a r5f52105bgfn r5f52105bgfn#30 plqp0080kb-a r5f52105bgfm r5f52105bgfm#30 plqp0064kb-a r5f52105bgfl r5f52105bgfl#30 plqp0048kb-a r5f52105bgff r5f52105bgff#v0 plqp0080ja-a r5f52105bgfk r5f52105bgfk#30 plqp0064ga-a r5f52104bgfm r5f52104bgfm#30 plqp0064kb-a 96 kbytes 16 kbytes r5f52104bgfl r5f52104bgfl#30 plqp0048kb-a r5f52104bgff r5f52104bgff#v0 plqp0080ja-a r5f52103bgfm r5f52103bgfm#30 plqp0064kb-a 64 kbytes 12 kbytes r5f52103bgfl r5f52103bgfl#30 plqp0048kb-a r5f52103bgff r5f52103bgff#v0 plqp0080ja-a
r01ds0041ej0150 rev.1.50 page 11 of 221 oct 18, 2013 rx210 group 1. overview note: ? orderable part numbers are current as of when this manual was published. please make sure to refer to the relevant product page on the renesas website for the latest part numbers. note: ? please contact renesas electronics sales office for derat ing of operation under ta = +85c to +105c. derating is the systematic reduction of load for t he sake of improved reliability. note: ? orderable part numbers are current as of when this manual was published. please make sure to refer to the relevant product page on the renesas website for the latest part numbers. table 1.6 list of products chip version c: d version (ta = ? 40 to +85c) group part no. orderable part no. package rom capacity ram capacity e2 dataflash operating frequency (max.) operating temperature rx210 r5f52108cdfp r5f52108cdfp#30 plqp0100kb-a 512 kbytes 64 kbytes 8 kbytes 50 mhz ? 40 to +85c r5f52108cdfn r5f52108cdfn#30 plqp0080kb-a r5f52108cdfm r5f52108cdfm#30 plqp0064kb-a r5f52108cdlj r5f52108cdlj#u0 ptlg0100ja-a r5f52108cdff r5f52108cdff#v0 plqp0080ja-a r5f52108cdfk r5f52108cdfk#30 plqp0064ga-a r5f52107cdfp r5f52107cdfp#30 plqp0100kb-a 384 kbytes r5f52107cdfn r5f52107cdfn#30 plqp0080kb-a r5f52107cdfm r5f52107cdfm#30 plqp0064kb-a r5f52107cdlj r5f52107cdlj#u0 ptlg0100ja-a r5f52107cdff r5f52107cdff#v0 plqp0080ja-a r5f52107cdfk r5f52107cdfk#30 plqp0064ga-a table 1.7 list of products chip version c: g version (ta = ? 40 to +105c) group part no. orderable part no. package rom capacity ram capacity e2 dataflash operating frequency (max.) operating temperature rx210 r5f52108cgfp r5f52108cgfp#30 plqp0100kb-a 512 kbytes 64 kbytes 8 kbytes 50 mhz ? 40 to +105c r5f52108cgfn r5f52108cgfn#30 plqp0080kb-a r5f52108cgfm r5f52108cgfm#30 plqp0064kb-a r5f52108cgff r5f52108cgff#v0 plqp0080ja-a r5f52108cgfk r5f52108cgfk#30 plqp0064ga-a r5f52107cgfp r5f52107cgfp#30 plqp0100kb-a 384 kbytes r5f52107cgfn r5f52107cgfn#30 plqp0080kb-a r5f52107cgfm r5f52107cgfm#30 plqp0064kb-a r5f52107cgff r5f52107cgff#v0 plqp0080ja-a r5f52107cgfk r5f52107cgfk#30 plqp0064ga-a
r01ds0041ej0150 rev.1.50 page 12 of 221 oct 18, 2013 rx210 group 1. overview figure 1.1 how to read the product part no., memory capacity, and package type r5f52108adfp #v0 production identification code packing, terminal material (pb-free) #3 : tray/sn (tin) only #v : tray/sn (tin) only #u : tray/sncu and others package type, number of pins, and pin pitch fb : lqfp/144/0.50 fp : lqfp/100/0.50 fn: lqfp/80/0.50 fm: lqfp/64/0.50 fl : lqfp/48/0.50 ff : lqfp/80/0.65 fk : lqfp/64/0.80 lk : tflga/145/0.50 la : tflga/100/0.50 lj : tflga/100/0.65 lh : tflga/64/0.65 bm: wlbga/69/0.40 d : operating temperature (?40 to +85c) g : operating temperature (?40 to +105c) chip version a:chip version a b:chip version b c:chip version c rom, ram, and e2 dataflash capacity b : 1 mbytes/96 kbytes/8 kbytes a : 768 kbytes/96 kbytes/8 kbytes 8 : 512 kbytes/64 kbytes/8 kbytes 7 : 384 kbytes/64 kbytes/8 kbytes 6 : 256 kbytes/32 kbytes/8 kbytes 5 : 128 kbytes/20 kbytes/8 kbytes 4 : 96 kbytes/16 kbytes/8 kbytes 3 : 64 kbytes/12 kbytes/8 kbytes group name 10 : rx210 group series name rx200 series type of memory f : flash memory version renesas mcu renesas semiconductor product
r01ds0041ej0150 rev.1.50 page 13 of 221 oct 18, 2013 rx210 group 1. overview 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram external bus bsc icub: interrupt controller dtca: data transfer controller dmaca: dma controller bsc: bus controller wdta: watchdog timer iwdta: independent watchdog timer elc: event link controller crc: crc (cyclic redundancy check) calculator scic, scid: serial communications interface rspi: serial peripheral interface riic: i 2 c bus interface tpua: 16-bit timer pulse unit mtu2a: multi-function timer pulse unit 2 poe2a: port output enable 2 tmr: 8-bit timer cmt: compare match timer rtcb: realtime clock doc: data operation circuit cac: clock frequency accuracy measurement circuit operand bus instruction bus internal main bus 1 clock generation circuit rx cpu ram rom port 7 port 8 port 9 port a port b 10-bit d/a converter 2 channels temperature sensor riic 1 channel doc wdta e2 dataflash crc elc rtcb mtu2a 6 channels 12-bit a/d converter 16 channels cmt 2 channels (unit 1) cmt 2 channels (unit 0) tmr 2 channels (unit 1) tmr 2 channels (unit 0) rspi 1 channel internal peripheral buses 1 to 6 internal main bus 2 dtca dmaca 4 channels icub cac scid 1 channel port c port d port e port f port h port j port k port l poe2a iwdta comparator b 2 channels comparator a 2 channels port 3 port 4 port 5 port 6 port 0 port 1 port 2 scic 12 channels tpua 6 channels
r01ds0041ej0150 rev.1.50 page 14 of 221 oct 18, 2013 rx210 group 1. overview 1.4 pin functions table 1.8 lists the pin functions. table 1.8 pin functions (1 / 4) classifications pin name i/o description power supply vcc input power supply pin. connect it to the system power supply. vcl ? connect this pin to the vss pin via the 0.1 f smoothing capacitor used to stabilize the internal power supply. place the capacitor close to the pin. vss input ground pin. connect it to the system power supply (0 v). clock xtal output pins for connecting a crystal resonator. an external clock signal can be input through the extal pin. extal input bclk output outputs the external bus clock for external devices. xcin input input/output pins for the sub- clock oscillator. connect a crystal resonator between xcin and xcout. xcout output operating mode control md input pin for setting the operating mode. the signal levels on this pin must not be changed during operation. system control res# input reset pin. this lsi enters the reset state when this signal goes low. cac cacref input input pin for the clock frequency accuracy measurement circuit. on-chip emulator fined i/o fine interface pin. address bus a0 to a23 output output pins for the address. data bus d0 to d15 i/o input and output pins for the bidirectional data bus. multiplexed bus a0/d0 to a15/d15 i/o address/data multiplexed bus bus control rd# output strobe signal which indi cates that reading from the external bus interface space is in progress. wr# output strobe signal which indicates that writing to the external bus interface space is in progress, in single-write strobe mode. wr0#, wr1# output strobe signals which indicate that either group of data bus pins (d7 to d0, and d15 to d8) is valid in wr iting to the external bus interface space, in byte strobe mode. bc0#, bc1# output strobe signals which indicate that either group of data bus pins (d7 to d0 and d15 to d8) is valid in access to the external bus interface space, in single-write strobe mode. cs0# to cs3# output select signals for areas 0 to 3. wait# input input pin for wait request signal s in access to the external space. ale output address latch signal when address/data multiplexed bus is selected. interrupt nmi input non-maskable interrupt request pin. irq0 to irq7 input interrupt request pins.
r01ds0041ej0150 rev.1.50 page 15 of 221 oct 18, 2013 rx210 group 1. overview 16-bit timer pulse unit tioca0, tiocb0 tiocc0, tiocd0 i/o the tgra0 to tgrd0 input capture input/output compare output/ pwm output pins. tioca1, tiocb1 i/o the tgra1 and tgrb1 input capture input/output compare output/ pwm output pins. tioca2, tiocb2 i/o the tgra2 and tgrb2 input capture input/output compare output/ pwm output pins. tioca3, tiocb3 tiocc3, tiocd3 i/o the tgra3 to tgrd3 input capture input/output compare output/ pwm output pins. tioca4, tiocb4 i/o the tgra4 and tgrb4 input capture input/output compare output/ pwm output pins. tioca5, tiocb5 i/o the tgra5 and tgrb5 input capture input/output compare output/ pwm output pins. tclka, tclkb tclkc, tclkd input input pins for external clock signals. multi-function timer pulse unit 2 mtioc0a, mtioc0b mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/ pwm output pins. mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/ pwm output pins. mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/ pwm output pins. mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output/ pwm output pins. mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output/ pwm output pins. mtic5u, mtic5v, mtic5w input the tgru5, tgrv5, and tgrw5 input capture input/external pulse input pins. mtclka, mtclkb, mtclkc, mtclkd input input pins for the external clock. port output enable 2 poe0# to poe3#, poe8# input input pins for request signals to place the mtu pins in the high impedance state. 8-bit timer tmo0 to tmo3 output compare match output pins. tmci0 to tmci3 input input pins for external clocks to be input to the counter. tmri0 to tmri3 input input pins for the counter reset. realtime clock rtcout output output pin for 1-hz clock. rtcic0 to rtcic2 input time capture event input pins. serial communications interface (scic) ? asynchronous mode/clock synchronous mode sck0 to sck11 i/o input/output pins for the clock rxd0 to rxd11 input input pins for received data txd0 to txd11 output output pins for transmitted data cts0# to cts11# input input pins for controll ing the start of transmission and reception rts0# to rts11# output output pins for contro lling the start of transmission and reception ? simple i 2 c mode sscl0 to sscl11 i/o input/output pins for the i 2 c clock ssda0 to ssda11 i/o input/output pins for the i 2 c data ? simple spi mode sck0 to sck11 i/o input/output pins for the clock smiso0 to smiso11 i/o input/output pins for slave transmission of data smosi0 to smosi11 i/o input/output pi ns for master transmission of data ss0# to ss11# input chip-select input pins table 1.8 pin functions (2 / 4) classifications pin name i/o description
r01ds0041ej0150 rev.1.50 page 16 of 221 oct 18, 2013 rx210 group 1. overview serial communications interface (scid) ? asynchronous mode/clock synchronous mode sck12 i/o input/output pin for the clock rxd12 input input pin for received data txd12 output output pin for transmitted data cts12# input input pin for controlling t he start of transmission and reception rts12# output output pin for controlling the start of transmission and reception ? simple i 2 c mode sscl12 i/o input/output pin for the i 2 c clock ssda12 i/o input/output pin for the i 2 c data ? simple spi mode sck12 i/o input/output pin for the clock smiso12 i/o input/output pin for slave transmit data smosi12 i/o input/output pin for master transmit data ss12# input chip-select input pin ? extended serial mode rxdx12 input input pin for data reception by scid txdx12 output output pin for data transmission by scid siox12 i/o input/output pin for data reception or transmission by scid i 2 c bus interface scl i/o input/output pin for i 2 c bus interface clocks. bus can be directly driven by the n-channel open-drain output. sda i/o input/output pin for i 2 c bus interface data. bus can be directly driven by the n-channel open-drain output. serial peripheral interface rspcka i/o clock input/output pin for the rspi. mosia i/o input or output data output from the master for the rspi. misoa i/o input or output data output from the slave for the rspi. ssla0 i/o input/output pin to select the slave for the rspi. ssla1 to ssla3 output output pins to select the slave for the rspi. 12-bit a/d converter an000 to an015 input input pins for the analog signals to be processed by the a/d converter. adtrg0# input input pin for the external trigger signals that start the a/d conversion. d/a converter da0, da1 output output pins for t he analog signals to be processed by the d/a converter. comparator a cmpa1 input input pin for the comparator a1 analog signal. cmpa2 input input pin for the comparator a2 analog signal. cvrefa input input pin for the comparator reference voltage. comparator b cmpb0 input input pin for the comparator b0 analog signal. cvrefb0 input input pin for the comparator b0 reference voltage. cmpb1 input input pin for the comparator b1 analog signal. cvrefb1 input input pin for the comparator b1 reference voltage. table 1.8 pin functions (3 / 4) classifications pin name i/o description
r01ds0041ej0150 rev.1.50 page 17 of 221 oct 18, 2013 rx210 group 1. overview analog power supply avcc0 input analog voltage supply pin for the 12-bit a/d converter. connect this pin to vcc if the 12-bit a/d converter is not to be used. avss0 input analog ground pin for the 12-bit a/d converter. connect this pin to vss if the 12-bit a/d converter is not to be used. vrefh0 input analog reference voltage supply pin for the 12-bit a/d converter. connect this pin to vcc if the 12-bit a/d converter is not to be used. vrefl0 input analog reference ground pin for the 12-bit a/d converter. connect this pin to vss if the 12-bit a/d converter is not to be used. vrefh input analog voltage supply pin for the d/a converter. connect this pin to vcc if the d/a converter is not to be used. vrefl input analog ground pin for the d/a converter. connect this pin to vss if the d/a converter is not to be used. i/o ports p00 to p03, p05, p07 i/o 6-bit input/output pins. p12 to p17 i/o 6-bit input/output pins. p20 to p27 i/o 8-bit input/output pins. p30 to p37 i/o 8-bit input/output pins. (p35 input pin) p40 to p47 i/o 8-bit input/output pins. p50 to p56 i/o 7-bit input/output pins. p60 to p67 i/o 8-bit input/output pins. p70 to p77 i/o 8-bit input/output pins. p80 to p83, p86, p87 i/o 6-bit input/output pins. p90 to p93 i/o 4-bit input/output pins. pa0 to pa7 i/o 8-bit input/output pins. pb0 to pb7 i/o 8-bit input/output pins. pc0 to pc7 i/o 8-bit input/output pins. pd0 to pd7 i/o 8-bit input/output pins. pe0 to pe7 i/o 8-bit input/output pins. pf5 i/o 1-bit input/output pin. ph0 to ph3 i/o 4-bit input/output pins. pj1, pj3, pj5 i/o 3-bit input/output pins. pk2 to pk5 i/o 4-bit input/output pins. pl0, pl1 i/o 2-bit input/output pins. table 1.8 pin functions (4 / 4) classifications pin name i/o description
r01ds0041ej0150 rev.1.50 page 18 of 221 oct 18, 2013 rx210 group 1. overview 1.5 pin assignments figure 1.3 to figure 1.11 show the pin assignments. table 1.9 to table 1.17 show the lists of pins and pin functions. figure 1.3 pin assignments of the 145-pin tflga (upper perspective view) p44 rx210 group ptlg0145ka-a (145-pin tflga) (upper perspective view) vss vcl pj5 nc pa0 p66 p65 p67 xcin xcout pj3 pj1 pa3 vss pa1 pa2 xtal res# md nc pa5 pa6 vcc pa4 extal vcc vss p35 p72 p71 pb0 pa7 p34 p33 p32 p30 pb3 pb4 pb2 pb1 p27 p26 p31 p15 p54 p53 p51 vcc p80 p76 pb7 pb6 pb5 p25 p23 p16 p24 p13 p56 p52 p83 pc5 pc4 pc2 p73 pl0 p22 p17 p86 p12 ph3 ph0 p50 pc6 p81 p77 pc0 pc1 pl1 p21 p20 p87 p14 ph2 ph1 p55 vss pc7 p82 pc3 p75 p74 13 12 11 10 9 8 7 6 5 4 3 2 1 bcdefghj klmn a bcdefghj klmn a 13 12 11 10 9 8 7 6 5 4 3 2 1 vrefl p02 vrefh0 p41 p46 vss pd1 pd3 pd7 p63 pe0 p70 pk4 vrefh avcc0 p05 vrefl0 p43 p47 p91 pd0 pd4 pk2 p61 pe2 pe4 avss0 p07 p40 p42 p45 p90 p92 pd2 pk3 p62 pe1 pe3 pd6 p00 pf5 p03 p01 vcc p93 pd5 p60 p64 pe7 pk5 pe5 pe6 note: ? this figure indicates the power supply pins and i/o port pi ns. for the pin configuration, see the table ?list of pins and pin functions (145-pin tflga)?. note: ? for the position of a1 pin in the package, see ?package dimensions?.
r01ds0041ej0150 rev.1.50 page 19 of 221 oct 18, 2013 rx210 group 1. overview figure 1.4 pin assignments of the 144-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 pe0 p64 p63 p62 p61 pk3 p60 pk2 pd7 pd6 pd5 pd4 pd2 pd1 pd0 p93 p92 p91 vss p90 vcc p47 p46 p45 p44 p43 p42 p41 vrefl0 p40 vrefh0 p07 pe1 pd3 avcc0 p74 pc2 p76 p77 pc3 pc4 p80 p81 p82 pc5 pc6 pc7 vcc vss p50 p51 p52 p53 p54 p55 p56 ph0 ph1 ph2 ph3 p12 p13 p14 p15 p86 p16 p87 p20 p75 p83 p17 pe3 pe5 pk4 p70 pk5 pe6 pe7 p65 p66 p67 pa0 pa1 pa2 vss pa4 vcc pa5 pa6 pa7 pb0 p71 p72 pb1 pb2 pb3 pb4 pb5 pb6 pb7 p73 pl0 pc0 pc1 pe4 pa3 pl1 avss0 vrefh p03 vrefl p02 p01 p00 pf5 nc pj5 vss pj3 vcl md xcin xcout res# p37/xtal vss p36/extal vcc p35 p34 p32 p31 p30 p27 p26 p25 p24 p23 p21 p05 pj1 p22 p33 pe2 rx210 group plqp0144ka-a (144-pin lqfp) (top view) note: ? this figure indicates the power supply pins and i /o port pins. for the pin configuration, see the table ?list of pins and pin functions (144-pin lqfp)?.
r01ds0041ej0150 rev.1.50 page 20 of 221 oct 18, 2013 rx210 group 1. overview figure 1.5 pin assignments of the 100-pin tflga (upper perspective view) pe2 rx210 group ptlg0100ja-a (100-pin tflga) (upper perspective view) pe1 pe0 pd4 pd0 p43 vrefl0 p07 vrefh p05 pe3 pd7 pd6 pd3 pd1 p44 p40 avcc0 avss0 p03 pe4 pe5 pd5 pd2 p47 p42 vrefh0 pj3 vrefl vcl pa0 pa1 pe7 pe6 p46 p45 pj1 md xcout xcin pa3 pa5 pa4 pa6 pa2 p41 p34 res# vss p37/ xtal vss pa7 pb0 pb2 pb3 p12 p32 p35 vcc p36/ extal vcc pb1 pb4 pb5 p52 p53 p27 p30 p31 p33 pb7 pb6 pc6 pc7 p54 p55 p15 p16 p25 p26 p17 pc1 pc0 pc4 p50 ph3 ph0 p13 p21 p24 pc2 pc3 pc5 p51 ph1 ph2 p14 p20 p22 p23 k j h g f e d c b a 10987654321 k j h g f e d c b a 10987654321 note: ? this figure indicates the power supply pins and i/o port pins . for the pin configuration, see the table ?list of pins and pin functions (100-pin tflga)?. note: ? for the position of a1 pin in the package, see ?package dimensions?.
r01ds0041ej0150 rev.1.50 page 21 of 221 oct 18, 2013 rx210 group 1. overview figure 1.6 pin assignments of the 100-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pe0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 p47 p46 p45 p43 p42 p41 vrefl0 p40 vrefh0 avcc0 p07 avss0 pe1 p44 pc2 pc4 pc5 pc6 pc7 p50 p51 p52 p53 p54 p55 ph0 ph1 ph3 p12 p13 p14 p15 p16 p17 p20 p21 p22 pc3 ph2 pe3 pe5 pe6 pe7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vss vcc pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pe4 pb0 vrefh vrefl pj3 vcl pj1 md xcin xcout res# p37/xtal vss p36/extal p35 p34 p33 p32 p31 p30 p27 p26 p25 p23 p03 vcc pe2 p05 p24 rx210 group plqp0100kb-a (100-pin lqfp) (top view) note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (100-pin lqfp)?.
r01ds0041ej0150 rev.1.50 page 22 of 221 oct 18, 2013 rx210 group 1. overview figure 1.7 pin assignments of the 80-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 pe2 pe1 pe0 pd2 pd1 pd0 p47 p46 p45 p44 p43 p42 vrefl0 p40 vrefh0 avcc0 p07 avss0 p05 p41 pc2 pc4 pc5 pc6 pc7 p54 p55 ph0 ph1 ph2 ph3 p12 p13 p15 p16 p17 p20 p21 pc3 p14 pe3 pe4 pe5 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pb0 vcc pb1 pb2 pb3 pb4 pb5 pb6 pb7 vss vrefh vrefl vcl pj1 md xcin xcout res# p37/xtal vss p36/extal vcc p34 p32 p31 p30 p27 p26 p03 p35 rx210 group plqp0080kb-a (80-pin lqfp) (top view) note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (80-pin lqfp)?.
r01ds0041ej0150 rev.1.50 page 23 of 221 oct 18, 2013 rx210 group 1. overview figure 1.8 pin assignments of the 69-pin wlbga abcdefgh avss0 vcl xcin p05 p03 xcout md res# xtal vss extal vcc p31 p32 p35 p30 p26 p27 p17 p14 ph3 ph1 p55 pc6 p54 pc5 pc3 pb6 nc pb3 pb1 pa1 pa4 pb0 pa0 pe4 pe3 p42 pe0 pe1 p44 p46 vrefh vrefl p43 pe2 p41 vrefl0 avcc0 vrefh0 avss0 p40 j nc p16 p15 ph2 ph0 pc7 pc4 pc2 pb7 pb5 vcc vss pa3 pa6 pe5 nc nc 1 2 3 4 5 6 7 8 9 rx210 group swbg0069la-a (69-pin wlbga) (top view) abcdefgh j 1 2 3 4 5 6 7 8 9 note: ? this figure indicates the power supply pins and i/o ports. for the pin configuration, see the table ?list of pins and pin functions (69-pin wlbga)?. note: ? for the position of a1 pin in the package, see ?package dimensions?. note: ? leave the nc pin open.
r01ds0041ej0150 rev.1.50 page 24 of 221 oct 18, 2013 rx210 group 1. overview figure 1.9 pin assignments of the 64-pin tflga a b c d e f g h 1 2 3 4 5 6 7 8 rx210 group ptlg0064ja-a (64-pin tflga) (upper perspective view) p05 avcc0 vrefh0 avss0 p40 vrefl0 p41 p42 p43 p44 vrefh p46 vrefl pe0 pe1 pe2 pe3 pe4 pe5 pa0 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pb6 pb7 pc2 pc3 pc4 pc5 pc6 pc7 p54 p55 ph0 ph2 ph1 ph3 p14 p15 p16 p17 p26 p27 p30 p31 p32 p35 vcc p36/ extal vss p37/ xtal res# xcout xcin md vcl p03 note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (64-pin tflga)?. note: ? for the position of a1 pin in the package, see ?package dimensions?.
r01ds0041ej0150 rev.1.50 page 25 of 221 oct 18, 2013 rx210 group 1. overview figure 1.10 pin assignments of the 64-pin lqfp 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx210 group plqp0064kb-a (64-pin lqfp) (top view) pe2 pe1 pe0 vrefl p46 vrefh p44 p43 p42 p41 vrefl0 p40 vrefh0 avcc0 p05 avss0 pe3 pe4 pe5 pa0 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pb6 pb7 pc2 pc3 pc4 pc5 pc6 pc7 p54 p55 ph0 ph1 ph2 ph3 p14 p15 p16 p17 p03 vcl md xcin xcout res# p37/xtal vss p36/extal vcc p35 p32 p31 p30 p27 p26 note: ? this figure indicates the power s upply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (64-pin lqfp)?.
r01ds0041ej0150 rev.1.50 page 26 of 221 oct 18, 2013 rx210 group 1. overview figure 1.11 pin assignments of the 48-pin lqfp 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 38 39 37 40 41 42 43 44 45 47 48 46 rx210 group plqp0048kb-a (48-pin lqfp) (top view) pe2 pe1 vrefl p46 vrefh p42 p41 vrefl0 p40 vrefh0 avcc0 avss0 pe3 pe4 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pc4 pc5 pc6 pc7 ph0 ph1 ph2 ph3 p14 p15 p16 p17 vcl md res# p37/xtal vss p36/extal vcc p35 p31 p30 p27 p26 18 17 16 15 14 13 note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (48-pin lqfp)?.
r01ds0041ej0150 rev.1.50 page 27 of 221 oct 18, 2013 rx210 group 1. overview table 1.9 list of pins and pin functions (145-pin tflga) (1 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others a1 avss0 a2 p07 adtrg0# a3 p40 an000 a4 p42 an002 a5 p45 an005 a6 p90 txd7/smosi7/ssda7 a7 p92 rxd7/smiso7/sscl7 a8 pd2 d2[a2/d2] mtioc4d irq2 a9 pd6 d6[a6/d6] mtic5v/poe1# irq6 a10 pk3 rxd9/smiso9/sscl9 a11 p62 a12 pe1 d9[a9/d9] mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 a13 pe3 d11[a11/d11] mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 b1 vrefh b2 avcc0 b3 p05 da1 b4 vrefl0 b5 p43 an003 b6 p47 an007 b7 p91 sck7 b8 pd0 d0[a0/d0] irq0 b9 pd4 d4[a4/d4] poe3# irq4 b10 pk2 txd9/smosi9/ssda9 b11 p61 cts9#/rts9#/ss9# b12 pe2 d10[a10/d10] mtioc4a rxd12/rxdx12/ smiso12/sscl12 irq7-ds/an010/ cvrefb0 b13 pe4 d12[a12/d12] mtioc4d/mtioc1a an012/cmpa2 c1 vrefl c2 p02 tmci1 sck6 c3 vrefh0 c4 p41 an001 c5 p46 an006 c6 vss c7 pd1 d1[a1/d1] mtioc4b irq1 c8 pd3 d3[a3/d3] poe8# irq3 c9 pd7 d7[a7/d7] mtic5u/poe0# irq7 c10 p63 c11 pe0 d8[a8/d8] sck12 an008 c12 p70 sck4 c13 pk4 rxd4/smiso4/sscl4 d1 p00 tmri0 txd6/smosi6/ssda6 d2 pf5 irq4 d3 p03 da0 d4 p01 tmci0 rxd6/smiso6/sscl6 d5 vcc d6 p93 cts7#/rts7#/ss7# d7 pd5 d5[a5/d5] mtic5w/poe2# irq5 d8 p60 sck9 d9 p64 d10 pe7 d15[a15/d15] irq7/an015
r01ds0041ej0150 rev.1.50 page 28 of 221 oct 18, 2013 rx210 group 1. overview d11 pk5 txd4/smosi4/ssda4 d12 pe5 d13[a13/d13] mtioc4c/mtioc2b irq5/an013 d13 pe6 d14[a14/d14] cts4#/rts4#/ss4# irq6/an014 e1 vss e2 vcl e3 pj5 e4 nc e5 p44 an004 e10 pa0 a0/bc0# mtioc4a/tioca0 ssla1 cacref e11 p66 e12 p65 e13 p67 f1 xcin f2 xcout f3 pj3 mtioc3c cts6#/rts6#/ss6#/ cts0#/rts0#/ss0# f4 pj1 mtioc3a f10 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb rxd5/smiso5/sscl 5irq6-ds/cmpb1 f11 vss f12 pa1 a1 mtioc0b/mtclkc/ tiocb0 sck5/ssla2 cvrefa f13 pa2 a2 rxd5/smiso5/sscl5/ ssla3 g1 xtal p37 g2 res# g3 md fined g4 nc g10 pa5 a5 tiocb1 rspcka g11 pa6 a6 mtic5v/mtclkb/ tmci3/poe2#/tioca2 cts5#/rts5#/ss5#/ mosia/ g12 vcc g13 pa4 a4 mtic5u/mtclka/ tmri0/tioca1 txd5/smosi5/ssda5/ ssla0 irq5-ds/cvrefb1 h1 extal p36 h2 vcc h3 vss h4 p35 nmi h10 p72 h11 p71 h12 pb0 a8 mtic5w/tioca3 rxd4/smiso4/sscl4/ rxd6/smiso6/sscl6/ rspcka h13 pa7 a7 tiocb2 misoa j1 p34 mtioc0a/tmci3/ poe2# sck6/sck0 irq4 j2 p33 mtioc0d/tmri3/ poe3#/tiocd0 rxd6/smiso6/sscl6/ rxd0/smiso0/sscl0 irq3-ds j3 p32 mtioc0c/tmo3/ tiocc0 txd6/smosi6/ssda6/ txd0/smosi0/ssda0 irq2-ds/rtcout/ rtcic2 j4 p30 mtioc4b/tmri3/ poe8# rxd1/smiso1/sscl1 irq0-ds/rtcic0 j10 pb3 a11 mtioc0a/mtioc4a/ tmo0/poe3#/ tiocd3/tclkd sck4/sck6 j11 pb4 a12 tioca4 cts9#/rts9#/ss9# table 1.9 list of pins and pin functions (145-pin tflga) (2 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 29 of 221 oct 18, 2013 rx210 group 1. overview j12 pb2 a10 tiocc3/tclkc cts4#/rts4#/ss4#/ cts6#/rts6#/ss6# j13 pb1 a9 mtioc0c/mtioc4c/ tmci0/tiocb3 txd4/smosi4/ssda4/ txd6/smosi6/ssda6 irq4-ds k1 p27 cs3# mtioc2b/tmci3 sck1 k2 p26 cs2# mtioc2a/tmo1 txd1/smosi1/ssda1/ cts3#/rts3#/ss3# k3 p31 mtioc4d/tmci2 cts1#/ rts1#/ss1# irq1-ds/rtcic1 k4 p15 mtioc0b/mtclkb/ tmci2/tiocb2/tclkb rxd1/smiso1/sscl1/ sck3 irq5 k5 p54 ale mtioc4b/tmci1 cts2#/rts2#/ss2# k6 bclk p53 k7 p51 wr1#/bc1#/wait# sck2 k8 vcc k9 p80 mtioc3b sck10 k10 p76 rxd11/smiso11/sscl11 k11 pb7 a15 mtioc3b/tiocb5 txd9/smosi9/ssda9 k12 pb6 a14 mtioc3d/tioca5 rxd9/smiso9/sscl9 k13 pb5 a13 mtioc2a/mtioc1b/ tmri1/poe1#/tiocb4 sck9 l1 p25 cs1# mtioc4c/mtclkb/ tioca4 rxd3/smiso3/sscl3 adtrg0# l2 p23 mtioc3d/mtclkd/ tiocd3 cts0#/rts0#/ss0#/ txd3/smosi3/ssda3 l3 p16 mtioc3c/mtioc3d/ tmo2/tiocb1/tclkc txd1/smosi1/ssda1/ mosia/scl-ds/rxd3/ smiso3/sscl3 irq6/rtcout/ adtrg0# l4 p24 cs0# mtioc4a/mtclka/ tmri1/tiocb4 sck3 l5 p13 mtioc0b/tmo3/ tioca5 sda/txd2/smosi2/ ssda2 irq3 l6 p56 mtioc3c/tioca1 l7 p52 rd# rxd2/smiso2/sscl2 l8 p83 mtioc4c cts10#/rts10# l9 pc5 a21/cs2#/wait# mtioc3b/mtclkd/ tmri2 sck8/rspcka l10 pc4 a20/cs3# mtioc3d/mtclkc/ tmci1/poe0# sck5/cts8#/rts8#/ ss8#/ssla0 l11 pc2 a18 mtioc4b/tclka rxd5/smiso5/sscl5/ ssla3 l12 p73 l13 pl0 m1 p22 mtioc3b/mtclkc/ tmo0/tiocc3 sck0 m2 p17 mtioc3a/mtioc3b/ tmo1/poe8#/tiocb0/ tclkd sck1/misoa/sda-ds/ txd3/smosi3/ssda3 irq7 m3 p86 tioca0 m4 p12 tmci1 scl/rxd2/smiso2/ sscl2 irq2 m5 ph3 tmci0 m6 ph0 cacref m7 p50 wr0#/wr# txd2/smosi2/ssda2 m8 pc6 a22/cs1# mtioc3c/mtclka/ tmci2 rxd8/smiso8/sscl8/ mosia m9 p81 mtioc3d rxd10/smiso10/sscl10 m10 p77 txd11/smosi11/ssda11 table 1.9 list of pins and pin functions (145-pin tflga) (3 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 30 of 221 oct 18, 2013 rx210 group 1. overview note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. note: ? leave the nc pin open. m11 pc0 a16 mtioc3c/tclkc cts5#/rts5#/ss5#/ ssla1 m12 pc1 a17 mtioc3a/tclkd sck5/ssla2 m13 pl1 n1 p21 mtioc1b/tmci0/ tioca3 rxd0/smiso0/sscl0 n2 p20 mtioc1a/tmri0/ tiocb3 txd0/smosi0/ssda0 n3 p87 tioca2 n4 p14 mtioc3a/mtclka/ tmri2/tiocb5/tclka cts1#/rts1#/ss1# irq4 n5 ph2 tmri0 irq1 n6 ph1 tmo0 irq0 n7 p55 wait# mtioc4d/tmo3 n8 vss n9 pc7 a23/cs0# mtioc3a/tmo2/ mtclkb txd8/smosi8/ssda8/ misoa cacref n10 p82 mtioc4a txd10/smosi10/ssda10 n11 pc3 a19 mtioc4d/tclkb txd5/smosi5/ssda5 n12 p75 sck11 n13 p74 cts11#/rts11#/ss11# table 1.9 list of pins and pin functions (145-pin tflga) (4 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 31 of 221 oct 18, 2013 rx210 group 1. overview table 1.10 list of pins and pin functions (144-pin lqfp) (1 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others 1 avss0 2 p05 da1 3 vrefh 4 p03 da0 5 vrefl 6 p02 tmci1 sck6 7 p01 tmci0 rxd6/smiso6/sscl6 8 p00 tmri0 txd6/smosi6/ssda6 9 pf5 irq4 10 nc 11 pj5 12 vss 13 pj3 mtioc3c cts6#/rts6#/ss6#/ cts0#/rts0#/ss0# 14 vcl 15 pj1 mtioc3a 16 md fined 17 xcin 18 xcout 19 res# 20 xtal p37 21 vss 22 extal p36 23 vcc 24 p35 nmi 25 p34 mtioc0a/tmci3/ poe2# sck6/sck0 irq4 26 p33 mtioc0d/tmri3/ poe3#/tiocd0 rxd6/smiso6/sscl6/ rxd0/smiso0/sscl0 irq3-ds 27 p32 mtioc0c/tmo3/ tiocc0 txd6/smosi6/ssda6/ txd0/smosi0/ssda0 irq2-ds/rtcout/ rtcic2 28 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1-ds/rtcic1 29 p30 mtioc4b/tmri3/ poe8# rxd1/smiso1/sscl1 irq0-ds/rtcic0 30 p27 cs3# mtioc2b/tmci3 sck1 31 p26 cs2# mtioc2a/tmo1 txd1/smosi1/ssda1/ cts3#/rts3#/ss3# 32 p25 cs1# mtioc4c/mtclkb/ tioca4 rxd3/smiso3/sscl3 adtrg0# 33 p24 cs0# mtioc4a/mtclka/ tmri1/tiocb4 sck3 34 p23 mtioc3d/mtclkd/ tiocd3 cts0#/rts0#/ss0#/ txd3/smosi3/ssda3 35 p22 mtioc3b/mtclkc/ tmo0/tiocc3 sck0 36 p21 mtioc1b/tmci0/ tioca3 rxd0/smiso0/sscl0 37 p 2 0 mtioc1a/tmri0/ tiocb3 txd0/smosi0/ssda0 38 p17 mtioc3a/mtioc3b/ tmo1/poe8#/tiocb0/ tclkd sck1/misoa/sda-ds/ txd3/smosi3/ssda3 irq7 39 p87 tioca2
r01ds0041ej0150 rev.1.50 page 32 of 221 oct 18, 2013 rx210 group 1. overview 40 p16 mtioc3c/mtioc3d/ tmo2/tiocb1/tclkc txd1/smosi1/ssda1/ mosia/scl-ds/rxd3/ smiso3/sscl3 irq6/rtcout/ adtrg0# 41 p86 tioca0 42 p15 mtioc0b/mtclkb/ tmci2/tiocb2/tclkb rxd1/smiso1/sscl1/ sck3 irq5 43 p14 mtioc3a/mtclka/ tmri2/tiocb5/tclka cts1#/rts1#/ss1# irq4 44 p13 mtioc0b/tmo3/ tioca5 sda/txd2/smosi2/ ssda2 irq3 45 p12 tmci1 scl/rxd2/smiso2/ sscl2 irq2 46 ph3 tmci0 47 ph2 tmri0 irq1 48 ph1 tmo0 irq0 49 ph0 cacref 50 p56 mtioc3c/tioca1 51 p55 wait# mtioc4d/tmo3 52 p54 ale mtioc4b/tmci1 cts2#/rts2#/ss2# 53 bclk p53 54 p52 rd# rxd2/smiso2/sscl2 55 p51 wr1#/bc1#/wait# sck2 56 p50 wr0#/wr# txd2/smosi2/ssda2 57 vss 58 p83 mtioc4c cts10#/rts10# 59 vcc 60 pc7 a23/cs0# mtioc3a/tmo2/ mtclkb txd8/smosi8/ssda8/ misoa cacref 61 pc6 a22/cs1# mtioc3c/mtclka/ tmci2 rxd8/smiso8/sscl8/ mosia 62 pc5 a21/cs2#/wait# mtioc3b/mtclkd/ tmri2 sck8/rspcka 63 p82 mtioc4a txd10/smosi10/ssda10 64 p81 mtioc3d rxd10/smiso10/sscl10 65 p80 mtioc3b sck10 66 pc4 a20/cs3# mtioc3d/mtclkc/ tmci1/poe0# sck5/cts8#/rts8#/ ss8#/ssla0 67 pc3 a19 mtioc4d/tclkb txd5/smosi5/ssda5 68 p77 txd11/smosi11/ssda11 69 p76 rxd11/smiso11/sscl11 70 pc2 a18 mtioc4b/tclka rxd5/smiso5/sscl5/ issla3 71 p75 sck11 72 p74 cts11#/rts11#/ss11# 73 pc1 a17 mtioc3a/tclkd sck5/ssla2 74 pl1 75 pc0 a16 mt ioc3 c/tclkc cts5#/rts5#/ss5#/ ssla1 76 pl0 77 p73 78 pb7 a15 mtioc3b/tiocb5 txd9/smosi9/ssda9 79 pb6 a14 mtioc3d/tioca5 rxd9/smiso9/sscl9 80 pb5 a13 mtioc2a/mtioc1b/ tmri1/poe1#/tiocb4 sck9 table 1.10 list of pins and pin functions (144-pin lqfp) (2 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 33 of 221 oct 18, 2013 rx210 group 1. overview 81 pb4 a12 tioca4 cts9#/rts9#/ss9# 82 pb3 a11 mtioc0a/mtioc4a/ tmo0/poe3#/ tiocd3/tclkd sck4/sck6 83 pb2 a10 tiocc3/tclkc cts4#/rts4#/ss4#/ cts6#/rts6#/ss6# 84 pb1 a9 mtioc0c/mtioc4c/ tmci0/tiocb3 txd4/smosi4/ssda4/ txd6/smosi6/ssda6 irq4-ds 85 p72 86 p71 87 pb0 a8 mtic5w/tioca3 rxd4/smiso4/sscl4/ rxd6/smiso6/sscl6/ rspcka 88 pa7 a7 tiocb2 misoa 89 pa6 a6 mtic5v/mtclkb/ tmci3/poe2#/tioca2 cts5#/rts5#/ss5#/ mosia/ 90 pa5 a5 tiocb1 rspcka 91 vcc 92 pa4 a4 mtic5u/mtclka/ tmri0/tioca1 txd5/smosi5/ssda5/ ssla0 irq5-ds/cvrefb1 93 vss 94 pa3 a3 mtioc0d/mtclkd/ tiocd0/tclkb rxd5/smiso5/sscl 5irq6-ds/cmpb1 95 pa2 a2 rxd5/smiso5/sscl5/ ssla3 96 pa1 a1 mtioc0b/mtclkc/ tiocb0 sck5/ssla2 cvrefa 97 pa0 a0/bc0# mtioc4a/tioca0 ssla1 cacref 98 p67 99 p66 100 p65 101 pe7 d15[a15/d15] irq7/an015 102 pe6 d14[a14/d14] cts4#/rts4#/ss4# irq6/an014 103 pk5 txd4/smosi4/ssda4 104 p70 sck4 105 pk4 rxd4/smiso4/sscl4 106 pe5 d13[a13/d13] mtioc4c/mtioc2b irq5/an013 107 pe4 d12[a12/d12] mtioc4d/mtioc1a an012/cmpa2 108 pe3 d11[a11/d11] mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 109 pe2 d10[a10/d10] mtioc4a rxd12/rxdx12/ smiso12/sscl12 irq7-ds/an010/ cvrefb0 110 pe1 d9[a9/d9] mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 111 pe0 d8[a8/d8] sck12 an008 112 p64 113 p63 114 p62 115 p61 cts9#/rts9#/ss9# 116 pk3 rxd9/smiso9/sscl9 117 p60 sck9 118 pk2 txd9/smosi9/ssda9 119 pd7 d7[a7/d7] mt ic5u/poe 0# irq7 120 pd6 d6[a6/d6] mtic5v/poe1# irq6 121 pd5 d5[a5/d5] mtic5w/poe2# irq5 table 1.10 list of pins and pin functions (144-pin lqfp) (3 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 34 of 221 oct 18, 2013 rx210 group 1. overview note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. note: ? leave the nc pin open. 122 pd4 d4[a4/d4] poe3# irq4 123 pd3 d3[a3/d3] poe8# irq3 124 pd2 d2[a2/d2] mtioc4d irq2 125 pd1 d1[a1/d1] mtioc4b irq1 126 pd0 d0[a0/d0] irq0 127 p93 cts7#/rts7#/ss7# 128 p92 rxd7/smiso7/sscl7 129 p91 sck7 130 vss 131 p90 txd7/smosi7/ssda7 132 vcc 133 p47 an007 134 p46 an006 135 p45 an005 136 p44 an004 137 p43 an003 138 p42 an002 139 p41 an001 140 vrefl0 141 p40 an000 142 vrefh0 143 avcc0 144 p07 adtrg0# table 1.10 list of pins and pin functions (144-pin lqfp) (4 / 4) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 35 of 221 oct 18, 2013 rx210 group 1. overview table 1.11 list of pins and pin functions (100-pin tflga) (1 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others a1 p05 da1 a2 vrefh a3 p07 adtrg0# a4 vrefl0 a5 p43 an003 a6 pd0 d0[a0/d0] irq0 a7 pd4 d4[a4/d4] poe3# irq4 a8 pe0 d8[a8/d8] sck12 an008 a9 pe1 d9[a9/d9] mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 a10 pe2 d10[a10/d10] mtioc4a rxd12/rxdx12/ smiso12/sscl12 irq7-ds/an010/ cvrefb0 b1 p03 da0 b2 avss0 b3 avcc0 b4 p40 an000 b5 p44 an004 b6 pd1 d1[a1/d1] mtioc4b irq1 b7 pd3 d3[a3/d3] poe8# irq3 b8 pd6 d6[a6/d6] mtic5v/poe1# irq6 b9 pd7 d7[a7/d7] mtic5u/poe0# irq7 b10 pe3 d11[a11/d11] mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 c1 vcl c2 vrefl c3 pj3 mtioc3c cts6#/rts6#/ss6# c4 vrefh0 c5 p42 an002 c6 p47 an007 c7 pd2 d2[a2/d2] mtioc4d irq2 c8 pd5 d5[a5/d5] mtic5w/poe2# irq5 c9 pe5 d13[a13/d13] mtioc4c/mtioc2b irq5/an013 c10 pe4 d12[a12/d12] mtioc4d/mtioc1a an012/cmpa2 d1 xcin d2 xcout d3 md fined d4 pj1 mtioc3a d5 p45 an005 d6 p46 an006 d7 pe6 d14[a14/d14] irq6/an014 d8 pe7 d15[a15/d15] irq7/an015 d9 pa1 a1 mtioc0b/mtclkc sck5/ssla2 cvrefa d10 pa0 a0/bc0# mtioc4a ssla1 cacref e1 xtal p37 e2 vss e3 res# e4 p34 mtioc0a/tmci3/ poe2# sck6 irq4 e5 p41 an001
r01ds0041ej0150 rev.1.50 page 36 of 221 oct 18, 2013 rx210 group 1. overview e6 pa2 a2 rxd5/smiso5/sscl5/ ssla3 e7 pa6 a6 mtic5v/mtclkb/ tmci3/poe2# cts5#/rts5#/ss5#/ mosia e8 pa4 a4 mtic5u/mtclka/ tmri0 txd5/smosi5/ssda5/ ssla0 irq5-ds/cvrefb1 e9 pa5 a5 rspcka e10 pa3 a3 mtioc0d/mtclkd rxd5 /smiso5/sscl5 irq6-ds/cmpb1 f1 extal p36 f2 vcc f3 p35 nmi f4 p32 mtioc0c/tmo3 txd6/smos i6/ssda6 irq2-ds/rtcout/ rtcic2 f5 p12 tmci1 scl irq2 f6 pb3 a11 mtioc0a/mtioc4a/ tmo0/poe3# sck6 f7 pb2 a10 cts6#/rts6#/ss6# f8 pb0 a8 mtic5w rxd6/smiso6/sscl6/ rspcka f9 pa7 a7 misoa f10 vss g1 p33 mtioc0d/tmri3/ poe3# rxd6/smiso6/sscl6 irq3-ds g2 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1-ds/rtcic1 g3 p30 mtioc4b/tmri3/ poe8# rxd1/smiso1/sscl1 irq0-ds/rtcic0 g4 p27 cs3# mtioc2b/tmci3 sck1 g5 bclk p53 g6 p52 rd# g7 pb5 a13 mtioc2a/mtioc1b/ tmri1/poe1# sck9 g8 pb4 a12 cts9#/rts9#/ss9# g9 pb1 a9 mtioc0c/mtioc4c/ tmci0 txd6/smosi6/ssda6 irq4-ds g10 vcc h1 p26 cs2# mtioc2a/tmo1 txd1/smosi1/ssda1 h2 p25 cs1# mtioc4c/mtclkb adtrg0# h3 p16 mtioc3c/mtioc3d/ tmo2 txd1/smosi1/ssda1/ mosia/scl-ds irq6/rtcout/ adtrg0# h4 p15 mtioc0b/mtclkb/ tmci2 rxd1/smiso1/sscl1 irq5 h5 p55 wait# mtioc4d/tmo3 h6 p54 ale mtioc4b/tmci1 h7 pc7 a23/cs0# mtioc3a/tmo2/ mtclkb txd8/smosi8/ssda8/ misoa cacref h8 pc6 a22/cs1# mtioc3c/mtclka/ tmci2 rxd8/smiso8/sscl8/ mosia h9 pb6 a14 mtioc3d rxd9/smiso9/sscl9 h10 pb7 a15 mtioc3b txd9/smosi9/ssda9 j1 p24 cs0# mtioc4a/mtclka/ tmri1 j2 p21 mtioc1b/tmci0 rxd0/smiso0/sscl0 j3 p17 mtioc3a/mtioc3b/ tmo1/poe8# sck1/misoa/ sda-ds irq7 table 1.11 list of pins and pin functions (100-pin tflga) (2 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 37 of 221 oct 18, 2013 rx210 group 1. overview note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. j4 p13 mtioc0b/tmo3 sda irq3 j5 ph0 cacref j6 ph3 tmci0 j7 p50 wr0#/wr# j8 pc4 a20/cs3# mtioc3d/mtclkc/ tmci1/poe0# sck5/cts8#/rts8#/ ss8#/ssla0 j9 pc0 a16 mtioc3c cts5#/rts5#/ss5#/ ssla1 j10 pc1 a17 mtioc3a sck5/ssla2 k1 p23 mtioc3d/mtclkd cts0#/rts0#/ss0# k2 p22 mtioc3b/mtclkc/ tmo0 sck0 k3 p20 mtioc1a/tmri0 txd0/smosi0/ssda0 k4 p14 mtioc3a/mtclka/ tmri2 cts1#/rts1#/ss1# irq4 k5 ph2 tmri0 irq1 k6 ph1 tmo0 irq0 k7 p51 wr1#/bc1#/wait# k8 pc5 a21/cs2#/wait# mtioc3b/mtclkd/ tmri2 sck8/rspcka k9 pc3 a19 mtioc4d txd5/smosi5/ssda5 k10 pc2 a18 mtioc4b rxd5/smiso5/sscl5/ ssla3 table 1.11 list of pins and pin functions (100-pin tflga) (3 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 38 of 221 oct 18, 2013 rx210 group 1. overview table 1.12 list of pins and pin functions (100-pin lqfp) (1 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others 1vrefh 2p03 da0 3vrefl 4 pj3 mtioc3c cts6#/rts6#/ss6# 5vcl 6pj1 mtioc3a 7md fined 8xcin 9 xcout 10 res# 11 xtal p37 12 vss 13 extal p36 14 vcc 15 p35 nmi 16 p34 mtioc0a/tmci3/ poe2# sck6 irq4 17 p33 mtioc0d/tmri3/ poe3# rxd6/smiso6/sscl6 irq3-ds 18 p32 mtioc0c/tmo3 txd6/smosi6/ssda6 irq2-ds/rtcout/ rtcic2 19 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1-ds/rtcic1 20 p30 mtioc4b/tmri3/ poe8# rxd1/smiso1/sscl1 irq0-ds/rtcic0 21 p27 cs3# mtioc2b/tmci3 sck1 22 p26 cs2# mtioc2a/tmo1 txd1/smosi1/ssda1 23 p25 cs1# mtioc4c/mtclkb adtrg0# 24 p24 cs0# mtioc4a/mtclka/ tmri1 25 p23 mtioc3d/mtclkd cts0#/rts0#/ss0# 26 p22 mtioc3b/mtclkc/ tmo0 sck0 27 p21 mtioc1b/tmci0 rxd0/smiso0/sscl0 28 p20 mtioc1a/tmri0 txd0/smosi0/ssda0 29 p17 mtioc3a/mtioc3b/ tmo1/poe8# sck1/misoa/ sda-ds irq7 30 p16 mtioc3c/mtioc3d/ tmo2 txd1/smosi1/ssda1/ mosia/scl-ds irq6/rtcout/ adtrg0# 31 p15 mtioc0b/mtclkb/ tmci2 rxd1/smiso1/sscl1 irq5 32 p14 mtioc3a/mtclka/ tmri2 cts1#/rts1#/ss1# irq4 33 p13 mtioc0b/tmo3 sda irq3 34 p12 tmci1 scl irq2 35 ph3 tmci0 36 ph2 tmri0 irq1 37 ph1 tmo0 irq0 38 ph0 cacref 39 p55 wait# mtioc4d/tmo3 40 p54 ale mtioc4b/tmci1 41 bclk p53
r01ds0041ej0150 rev.1.50 page 39 of 221 oct 18, 2013 rx210 group 1. overview 42 p52 rd# 43 p51 wr1#/bc1#/wait# 44 p50 wr0#/wr# 45 pc7 a23/cs0# mtioc3a/tmo2/ mtclkb txd8/smosi8/ssda8/ misoa cacref 46 pc6 a22/cs1# mtioc3c/mtclka/ tmci2 rxd8/smiso8/sscl8/ mosia 47 pc5 a21/cs2#/wait# mtioc3b/mtclkd/ tmri2 sck8/rspcka 48 pc4 a20/cs3# mtioc3d/mtclkc/ tmci1/poe0# sck5/cts8#/rts8#/ ss8#/ssla0 49 pc3 a19 mtioc4d txd5/smosi5/ssda5 50 pc2 a18 mtioc4b rxd5/smiso5/sscl5/ ssla3 51 pc1 a17 mtioc3a sck5/ssla2 52 pc0 a16 mtioc3c cts5#/rts5#/ss5#/ ssla1 53 pb7 a15 mtioc3b txd9/smosi9/ssda9 54 pb6 a14 mtioc3d rxd9/smiso9/sscl9 55 pb5 a13 mtioc2a/mtioc1b/ tmri1/poe1# sck9 56 pb4 a12 cts9#/rts9#/ss9# 57 pb3 a11 mtioc0a/mtioc4a/ tmo0/poe3# sck6 58 pb2 a10 cts6#/rts6#/ss6# 59 pb1 a9 mtioc0c/mtioc4c/ tmci0 txd6/smosi6/ssda6 irq4-ds 60 vcc 61 pb0 a8 mtic5w rxd6/smiso6/sscl6/ rspcka 62 vss 63 pa7 a7 misoa 64 pa6 a6 mtic5v/mtclkb/ tmci3/poe2# cts5#/rts5#/ss5#/ mosia 65 pa5 a5 rspcka 66 pa4 a4 mtic5u/mtclka/ tmri0 txd5/smosi5/ssda5/ ssla0 irq5-ds/cvrefb1 67 pa3 a3 mtioc0d/mtclkd rxd5/smiso5/sscl5 irq6-ds/cmpb1 68 pa2 a2 rxd5/smiso5/sscl5/ ssla3 69 pa1 a1 mtioc0b/mtclkc sck5/ssla2 cvrefa 70 pa0 a0/bc0# mtioc4a ssla1 cacref 71 pe7 d15[a15/d15] irq7/an015 72 pe6 d14[a14/d14] irq6/an014 73 pe5 d13[a13/d13] mtioc4c/mtioc2b irq5/an013 74 pe4 d12[a12/d12] mtioc4d/mtioc1a an012/cmpa2 75 pe3 d11[a11/d11] mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 76 pe2 d10[a10/d10] mtioc4a rxd12/rxdx12/ smiso12/sscl12 irq7-ds/an010/ cvrefb0 77 pe1 d9[a9/d9] mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 78 pe0 d8[a8/d8] sck12 an008 79 pd7 d7[a7/d7] mtic5u/poe0# irq7 table 1.12 list of pins and pin functions (100-pin lqfp) (2 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 40 of 221 oct 18, 2013 rx210 group 1. overview note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. 80 pd6 d6[a6/d6] mtic5v/poe1# irq6 81 pd5 d5[a5/d5] mtic5w/poe2# irq5 82 pd4 d4[a4/d4] poe3# irq4 83 pd3 d3[a3/d3] poe8# irq3 84 pd2 d2[a2/d2] mtioc4d irq2 85 pd1 d1[a1/d1] mtioc4b irq1 86 pd0 d0[a0/d0] irq0 87 p47 an007 88 p46 an006 89 p45 an005 90 p44 an004 91 p43 an003 92 p42 an002 93 p41 an001 94 vrefl0 95 p40 an000 96 vrefh0 97 avcc0 98 p07 adtrg0# 99 avss0 100 p05 da1 table 1.12 list of pins and pin functions (100-pin lqfp) (3 / 3) pin no. power supply, clock, system control i/o port external bus timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 41 of 221 oct 18, 2013 rx210 group 1. overview table 1.13 list of pins and pin functions (80-pin lqfp) (1 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others 1vrefh 2p03 da0 3vrefl 4vcl 5pj1mtioc3a 6md fined 7xcin 8 xcout 9res# 10 xtal p37 11 vss 12 extal p36 13 vcc 14 p35 nmi 15 p34 mtioc0a/tmci3/poe2# sck6 irq4 16 p32 mtioc0c/tmo3 txd6/smosi6/ssda6 irq2-ds/rtcout/ rtcic2 17 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1-ds/rtcic1 18 p30 mtioc4b/tmri3/poe8# rxd1 /smiso1/sscl1 irq0-ds/rtcic0 19 p27 mtioc2b/tmci3 sck1 20 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 21 p21 mtioc1b/tmci0 rxd0/sscl0 22 p20 mtioc1a/tmri0 txd0/ssda0 23 p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/ sda-ds irq7 24 p16 mtioc3c/mtioc3d/tmo2 t xd1/smosi1/ssda1/mosia/ scl-ds irq6/rtcout/ adtrg0# 25 p15 mtioc0b/mtclkb/tmci2 rxd1/smiso1/sscl1 irq5 26 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# irq4 27 p13 mtioc0b/tmo3 sda irq3 28 p12 tmci1 scl irq2 29 ph3 tmci0 30 ph2 tmri0 irq1 31 ph1 tmo0 irq0 32 ph0 cacref 33 p55 mtioc4d/tmo3 34 p54 mtioc4b/tmci1 35 pc7 mtioc3a/tmo2/mtclkb txd8 /smosi8/ssda8/misoa cacref 36 pc6 mtioc3c/mtclka/tmci 2 rxd8/smiso8/sscl8/mosia 37 pc5 mtioc3b/mtclkd/tmri2 sck8/rspcka 38 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ss8#/ ssla0 39 pc3 mtioc4d txd5/smosi5/ssda5 40 pc2 mtioc4b rxd5/smiso5/sscl5/ssla3 41 pb7 mtioc3b txd9/smosi9/ssda9 42 pb6 mtioc3d rxd9/smiso9/sscl9 43 pb5 mtioc2a/mtioc1b/tmri1/ poe1# sck9 44 pb4 cts9#/rts9#/ss9#
r01ds0041ej0150 rev.1.50 page 42 of 221 oct 18, 2013 rx210 group 1. overview note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. 45 pb3 mtioc0a/mtioc4a/tmo0/ poe3# sck6 46 pb2 cts6#/rts6#/ss6# 47 pb1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 irq4-ds 48 vcc 49 pb0 mtic5w rxd6/smiso6/sscl6/rspcka 50 vss 51 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia 52 pa5 rspcka 53 pa4 mtic5u/mtclka/tmri0 txd5/smo si5/ssda5/ssla0 irq5-ds/cvrefb1 54 pa3 mtioc0d/mtclkd rxd5/smiso5/sscl5 irq6-ds/cmpb1 55 pa2 rxd5/smiso5/sscl5/ssla3 56 pa1 mtioc0b/mtclkc sck5/ssla2 cvrefa 57 pa0 mtioc4a ssla1 cacref 58 pe5 mtioc4c/mtioc2b irq5/an013 59 pe4 mtioc4d/mtioc1a an012/cmpa2 60 pe3 mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 61 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12 irq7-ds/an010/ cvrefb0 62 pe1 mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 63 pe0 sck12 an008 64 pd2 mtioc4d irq2 65 pd1 mtioc4b irq1 66 pd0 irq0 67 p47 an007 68 p46 an006 69 p45 an005 70 p44 an004 71 p43 an003 72 p42 an002 73 p41 an001 74 vrefl0 75 p40 an000 76 vrefh0 77 avcc0 78 p07 adtrg0# 79 avss0 80 p05 da1 table 1.13 list of pins and pin functions (80-pin lqfp) (2 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 43 of 221 oct 18, 2013 rx210 group 1. overview table 1.14 list of pins and pin functions (69-pin wlbga) (1 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others a1 nc a2 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12 irq7-ds/an010/ cvrefb0 a3 vrefl a4 vrefh a5 p43 an003 a6 vrefl0 a7 avcc0 a8 avss0 a9 avss0 b1 pe5 mtioc4c/mtioc2b irq5/an013 b2 pe4 mtioc4d/mtioc1a an012/cmpa2 b3 pe3 mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 b4 p46 an006 b5 p44 an004 b6 p41 an001 b7 vrefh0 b8 p05 da1 b9 vcl c1 pa3 mtioc0d/mtclkd rxd5/ smiso5/sscl5 irq6-ds/cmpb1 c2 pa4 mtic5u/mtclka/tmri0 txd5/smosi5/ssda5/ssla0 irq5-ds/cvrefb1 c3 pa0 mtioc4a ssla1 cacref c4 pe1 mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 c5 pe0 sck12 an008 c6 p42 an002 c7 p40 an000 c8 p03 da0 c9 xcin d1 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia d2 pb0 mtic5w rxd6/smiso6/sscl6/ rspcka d3 pa1 mtioc0b/mtclkc sck5/ssla2 cvrefa d7 md fined d8 res# d9 xcout e1 vss e2 pb1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 irq4-ds e8 xtal p37 e9 vss f1 vcc f2 pb3 mtioc0a/mtioc4a/tmo0/ poe3# sck6 f7 p31 mtioc4d/tmci2 cts1#/ rts1#/ss1# irq1-ds/rtcic1 f8 extal p36 f9 vcc g1 pb5 mtioc2a/mtioc1b/tmri1/ poe1# sck9 g2 pb6 mtioc3d rxd9/smiso9/sscl9
r01ds0041ej0150 rev.1.50 page 44 of 221 oct 18, 2013 rx210 group 1. overview note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. note: ? leave the nc pin open. g3 nc g4 p54 mtioc4b/tmci1 g5 ph1 tmo0 irq0 g6 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# irq4 g7 p27 mtioc2b/tmci3 sck1 g8 p32 mtioc0c/tmo3 txd6/smos i6/ssda6 irq2-ds/rtcout/ rtcic2 g9 p35 nmi h1 pb7 mtioc3b txd9/smosi9/ssda9 h2 pc3 mtioc4d txd5/smosi5/ssda5 h3 pc5 mtioc3b/mtclkd/tmri2 sck8/rspcka h4 pc6 mtioc3c/mtclka/tmci2 rxd8/smiso8/sscl8/mosia h5 p55 mtioc4d/tmo3 h6 ph3 tmci0 h7 p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/sda-ds irq7 h8 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 h9 p30 mtioc4b/tmri3/poe8# rxd1 /smiso1/sscl1 irq0-ds/rtcic0 j1 nc j2 pc2 mtioc4b rxd5/smiso5/sscl5/ssla3 j3 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ss8#/ ssla0 j4 pc7 mtioc3a/tmo2/mtclkb txd8 /smosi8/ssda8/ misoa cacref j5 ph0 cacref j6 ph2 tmri0 irq1 j7 p15 mtioc0b/mtclkb/tmci2 rxd1/smiso1/sscl1 irq5 j8 p16 mtioc3c/mtioc3d/tmo2 txd1/smosi1/ssda1/ mosia/scl-ds irq6/rtcout/ adtrg0# j9 nc table 1.14 list of pins and pin functions (69-pin wlbga) (2 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 45 of 221 oct 18, 2013 rx210 group 1. overview table 1.15 list of pins and pin functions (64-pin tflga) (1 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communication (scic, scid, rspi, riic) others a1 p05 da1 a2 avcc0 a3 vrefh0 a4 vrefl0 a5 vrefh a6 vrefl a7 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12 irq7-ds/an010/ cvrefb0 a8 pe3 mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 b1 vcl b2 avss0 b3 p40 an000 b4 p42 an002 b5 p44 an004 b6 p46 an006 b7 pe1 mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 b8 pe4 mtioc4d/mtioc1a an012/cmpa2 c1 xcin c2 md fined c3 p03 da0 c4 p41 an001 c5 p43 an003 c6 pe0 sck12 an008 c7 pe5 mtioc4c/mtioc2b irq5/an013 c8 pa0 mtioc4a ssla1 cacref d1 xcout d2 res# d3 p27 mtioc2b/tmci3 sck1 d4 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# irq4 d5 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia d6 pa4 mtic5u/mtclka/tmri0 txd5/smo si5/ssda5/ssla0 irq5-ds/cvrefb1 d7 pa1 mtioc0b/mtclkc sck5/ssla2 cvrefa d8 pa3 mtioc0d/mtclkd rxd5/smiso5/sscl5 irq6-ds/cmpb1 e1 vss e2 p32 mtioc0c/tmo3 txd6/smosi6/ssda6 irq2-ds/rtcout/ rtcic2 e3 p30 mtioc4b/tmri3/poe8# rxd1 /smiso1/sscl1 irq0-ds/rtcic0 e4 p16 mtioc3c/mtioc3d/tmo2 t xd1/smosi1/ssda1/mosia/ scl-ds irq6/rtcout/ adtrg0# e5 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ss8#/ ssla0 e6 vcc e7 vss e8 pb0 mtic5w rxd6/smiso6/sscl6/rspcka f1 vcc f2 p35 nmi f3 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1-ds/rtcic1 f4 pc5 mtioc3b/mtclkd/tmri2 sck8/rspcka
r01ds0041ej0150 rev.1.50 page 46 of 221 oct 18, 2013 rx210 group 1. overview note: ? pin names to which -ds is appended are for pins that can be used to trigger release from deep software standby mode. f5 p15 mtioc0b/mtclkb/tmci2 rxd1/smiso1/sscl1 irq5 f6 pb1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 irq4-ds f7 pb5 mtioc2a/mtioc1b/tmri1/ poe1# sck9 f8 pb3 mtioc0a/mtioc4a/tmo0/ poe3# sck6 g1 extal p36 g2 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 g3 ph3 tmci0 g4 ph0 cacref g5 pc7 mtioc3a/tmo2/mtclkb txd8 /smosi8/ssda8/misoa cacref g6 pc6 mtioc3c/mtclka/tmci 2 rxd8/smiso8/sscl8/mosia g7 pc3 mtioc4d txd5/smosi5/ssda5 g8 pb6 mtioc3d rxd9/smiso9/sscl9 h1 xtal p37 h2 p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/sda-ds irq7 h3 ph2 tmri0 irq1 h4 ph1 tmo0 irq0 h5 p55 mtioc4d/tmo3 h6 p54 mtioc4b/tmci1 h7 pc2 mtioc4b rxd5/smiso5/sscl5/ssla3 h8 pb7 mtioc3b txd9/smosi9/ssda9 table 1.15 list of pins and pin functions (64-pin tflga) (2 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communication (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 47 of 221 oct 18, 2013 rx210 group 1. overview table 1.16 list of pins and pin functions (64-pin lqfp) (1 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communication (scic, scid, rspi, riic) others 1p 0 3 da0 2v c l 3m d fined 4x c i n 5 xcout 6r e s # 7x t a l p 3 7 8v s s 9 extal p36 10 vcc 11 p35 nmi 12 p32 mtioc0c/tmo3 txd6/smosi6/ssda6 irq2-ds/rtcout/ rtcic2 13 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1-ds/rtcic1 14 p30 mtioc4b/tmri3/poe8# rxd1 /smiso1/sscl1 irq0-ds/rtcic0 15 p27 mtioc2b/tmci3 sck1 16 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 17 p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/sda-ds irq7 18 p16 mtioc3c/mtioc3d/tmo2 t xd1/smosi1/ssda1/mosia/ scl-ds irq6/rtcout/ adtrg0# 19 p15 mtioc0b/mtclkb/tmci2 rxd1/smiso1/sscl1 irq5 20 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# irq4 21 ph3 tmci0 22 ph2 tmri0 irq1 23 ph1 tmo0 irq0 24 ph0 cacref 25 p55 mtioc4d/tmo3 26 p54 mtioc4b/tmci1 27 pc7 mtioc3a/tmo2/mtclkb txd8 /smosi8/ssda8/ misoa cacref 28 pc6 mtioc3c/mtclka/tmci 2 rxd8/smiso8/sscl8/mosia 29 pc5 mtioc3b/mtclkd/tmri2 sck8/rspcka 30 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ss8#/ ssla0 31 pc3 mtioc4d txd5/smosi5/ssda5 32 pc2 mtioc4b rxd5/smiso5/sscl5/ssla3 33 pb7 mtioc3b txd9/smosi9/ssda9 34 pb6 mtioc3d rxd9/smiso9/sscl9 35 pb5 mtioc2a/mtioc1b/tmri1/ poe1# sck9 36 pb3 mtioc0a/mtioc4a/tmo0/ poe3# sck6 37 pb1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 irq4-ds 38 vcc 39 pb0 mtic5w rxd6/smiso6/sscl6/rspcka 40 vss 41 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia 42 pa4 mtic5u/mtclka/tmri0 txd5/smosi5/ssda5/ssla0 irq5-ds/cvrefb1 43 pa3 mtioc0d/mtclkd rxd5/sm iso5/sscl5 irq6-ds/cmpb1
r01ds0041ej0150 rev.1.50 page 48 of 221 oct 18, 2013 rx210 group 1. overview note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. 44 pa1 mtioc0b/mtclkc sck5/ssla2 cvrefa 45 pa0 mtioc4a ssla1 cacref 46 pe5 mtioc4c/mtioc2b irq5/an013 47 pe4 mtioc4d/mtioc1a an012/cmpa2 48 pe3 mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 49 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12 irq7-ds/an010/ cvrefb0 50 pe1 mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009/cmpb0 51 pe0 sck12 an008 52 vrefl 53 p46 an006 54 vrefh 55 p44 an004 56 p43 an003 57 p42 an002 58 p41 an001 59 vrefl0 60 p40 an000 61 vrefh0 62 avcc0 63 p05 da1 64 avss0 table 1.16 list of pins and pin functions (64-pin lqfp) (2 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communication (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 49 of 221 oct 18, 2013 rx210 group 1. overview table 1.17 list of pins and pin functions (48-pin lqfp) (1 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communication (scic, scid, rspi, riic) others 1v c l 2m d fined 3r e s # 4x t a l p 3 7 5v s s 6 extal p36 7v c c 8p 3 5 nmi 9 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1-ds 10 p30 mtioc4b/tmri3/poe8# rxd1/smiso1/sscl1 irq0-ds 11 p27 mtioc2b/tmci3 sck1 12 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 13 p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/sda-ds irq7 14 p16 mtioc3c/mtioc3d/tmo2 t xd1/smosi1/ssda1/mosia/ scl-ds irq6/adtrg0# 15 p15 mtioc0b/mtclkb/tmci2 rxd1/smiso1/sscl1 irq5 16 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# irq4 17 ph3 tmci0 18 ph2 tmri0 irq1 19 ph1 tmo0 irq0 20 ph0 cacref 21 pc7 mtioc3a/tmo2/mtclkb txd8 /smosi8/ssda8/ misoa cacref 22 pc6 mtioc3c/mtclka/tmci 2 rxd8/smiso8/sscl8/mosia 23 pc5 mtioc3b/mtclkd/tmri2 sck8/rspcka 24 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/cts8#/rts8#/ss8#/ ssla0 25 pb5 mtioc2a/mtioc1b/tmri1/ poe1# 26 pb3 mtioc0a/mtioc4a/tmo0/ poe3# sck6 27 pb1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 irq4-ds 28 vcc 29 pb0 mtic5w rxd6/smiso6/sscl6/rspcka 30 vss 31 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia 32 pa4 mtic5u/mtclka/tmri0 txd5/smosi5/ssda5/ssla0 irq5-ds/cvrefb1 33 pa3 mtioc0d/mtclkd rxd5/sm iso5/sscl5 irq6-ds/cmpb1 34 pa1 mtioc0b/mtclkc sck5/ssla2 cvrefa 35 pe4 mtioc4d/mtioc1a an012/cmpa2 36 pe3 mtioc4b/poe8# cts12#/rts12# an011/cmpa1 37 pe2 mtioc4a rxd12/rxdx12/sscl12 irq7-ds/an010/ cvrefb0 38 pe1 mtioc4c txd12/txdx12/siox12/ ssda12 an009/cmpb0 39 vrefl 40 p46 an006 41 vrefh 42 p42 an002 43 p41 an001
r01ds0041ej0150 rev.1.50 page 50 of 221 oct 18, 2013 rx210 group 1. overview note: ? pin names to which ?ds is appended are for pins that c an be used to trigger release from deep software standby mode. 44 vrefl0 45 p40 an000 46 vrefh0 47 avcc0 48 avss0 table 1.17 list of pins and pin functions (48-pin lqfp) (2 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communication (scic, scid, rspi, riic) others
r01ds0041ej0150 rev.1.50 page 51 of 221 oct 18, 2013 rx210 group 2. cpu 2. cpu figure 2.1 shows the register set of the cpu. figure 2.1 register set of the cpu note 1. the stack pointer (sp) can be the interrupt stack pointer (isp) or user stack pointer (usp), according to the value of the u bit in the psw register. usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) *1 general-purpose register control register b31 b0 b31 b0 dsp instruction register b63 b0 acc (accumulator)
r01ds0041ej0150 rev.1.50 page 52 of 221 oct 18, 2013 rx210 group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has sixteen general-purpose registers (r0 to r15). r1 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by th e value of the stack pointer se lect bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer (i sp)/user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack point er (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack poi nter select bit (u) in the processor status word (psw). set the isp or usp to a multiple of four, as this reduces th e numbers of cycles required to execute interrupt sequences and instructions entai ling stack manipulation. (2) interrupt table register (intb) the interrupt table register (intb) specifies the address where the relocatable vector table starts. (3) program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. (4) processor status word (psw) the processor status word (psw) i ndicates the results of instruction execution or the state of the cpu. (5) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the program counter (pc) are saved in the bpc register. (6) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (7) fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated. 2.3 register associated with dsp instructions (1) accumulator (acc) the accumulator (acc) is a 64-bit register used for dsp instru ctions. the accumulator is also used for the multiply and multiply-and-accumulate inst ructions; emul, emulu, mul, and rmpa, in which case the prior value in the accumulator is modified by execution of the instruction. use the mvtachi and mvtaclo instructions for wr iting to the accumulator. the mvtachi and mvtaclo instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfachi and mvfacmi instructions for reading data from th e accumulator. the mvfachi and mvfacmi instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
r01ds0041ej0150 rev.1.50 page 53 of 221 oct 18, 2013 rx210 group 3. address space 3. address space 3.1 address space this lsi has a 4-gbyte address space, consisting of the rang e of addresses from 0000 0000 h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is po ssible, and this contains bo th program and data areas. figure 3.1 shows the memory maps in the re spective operating modes. accessible areas will differ according to the operating mode and stat es of control bits.
r01ds0041ej0150 rev.1.50 page 54 of 221 oct 18, 2013 rx210 group 3. address space figure 3.1 memory map in each operating mode reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 on-chip rom (e2 dataflash) (8 kb) reserved area* 3 0000 0000h 0008 0000h ffff ffffh single-chip mode* 1 ram* 2 on-chip rom (program rom) (read only)* 2 0010 0000h peripheral i/o registers 0010 2000h 0080 0000h 0100 0000h on-chip rom (program rom) (write only) (1 mb) fff0 0000h ff7f c000h on-chip rom (user boot) (read only) (16 kb) fcu-ram (8 kb) peripheral i/o registers peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0001 0000h ff80 0000h 00f0 0000h on-chip rom (fcu firmware) (read only) (8 kb) feff e000h ff00 0000h reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 0000 0000h 0008 0000h ffff ffffh on-chip rom enabled extended mode ram* 2 on-chip rom (program rom) (read only)* 2 0010 0000h peripheral i/o registers 0010 2000h on-chip rom (e2 dataflash) (8 kb) 0080 0000h 0100 0000h on-chip rom (program rom) (write only) (1 mb) 0800 0000h fff0 0000h ff7f c000h on-chip rom (user boot) (read only) (16 kb) fcu-ram (8 kb) peripheral i/o registers peripheral i/o registers 007f 8000h 007f a000h 007f c000h 007f c500h 007f fc00h 0001 0000h external address space ff80 0000h 00f0 0000h on-chip rom (fcu firmware) (read only) (8 kb) feff e000h ff00 0000h 0500 0000h reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode ram* 2 0010 0000h peripheral i/o registers 0100 0000h 0800 0000h ff00 0000h 0001 0000h external address space external address space 0500 0000h note 1. the address space in boot mode and user boot mode is the same as the address space in single-chip mode. note 2. the capacity of rom/ra m differs depending on the products. note:?see table 1.3 to table 1.7 list of products, for the product type name. note 3. reserved areas should not be accessed. rom (bytes) ram (bytes) capacity address capacity address 1 m fff0 0000h to ffff ffffh 96 k 0000 0000h to 0001 7fffh 768 k fff4 0000h to ffff ffffh 512 k fff8 0000h to ffff ffffh 64 k 0000 0000h to 0000 ffffh 384 k fffa 0000h to ffff ffffh 256 k fffc 0000h to ffff ffffh 32 k 0000 0000h to 0000 7fffh 128 k fffe 0000h to ffff ffffh 20 k 0000 0000h to 0000 4fffh 96 k fffe 8000h to ffff ffffh 16 k 0000 0000h to 0000 3fffh 64 k ffff 0000h to ffff ffffh 12 k 0000 0000h to 0000 2fffh
r01ds0041ej0150 rev.1.50 page 55 of 221 oct 18, 2013 rx210 group 3. address space 3.2 external address space the external address space is divided into up to four cs areas (cs0 to cs3) , each corresponding to the csn# signal output from a csn# (n = 0 to 3) pin. figure 3.2 shows the address ranges corresponding to the indivi dual cs areas (cs0 to cs3) in on-chip rom disabled extended mode. figure 3.2 correspondence between external address spaces and cs areas (in on-chip rom disabl ed extended mode) 0500 0000h 0600 0000h 0700 0000h cs3 (16 mb) 05ff ffffh 06ff ffffh 07ff ffffh cs2 (16 mb) cs1 (16 mb) ffff ffffh ff00 0000h cs0 (16 mb) note 1. reserved areas should not be accessed. note 2. the cs0 area is disabled in on-chip rom enabled extended mode. in this mode, the address space for addresses above 0800 0000h is as shown in figure on this section ?memory map in each operating mode?. reserved area* 1 reserved area* 1 reserved area* 1 reserved area* 1 0000 0000h 0008 0000h ffff ffffh on-chip rom disabled extended mode on-chip ram 0010 0000h peripheral i/o registers 0100 0000h 0800 0000h ff00 0000h 0001 0000h external address space* 2 external address space 0500 0000h
r01ds0041ej0150 rev.1.50 page 56 of 221 oct 18, 2013 rx210 group 4. i/o registers 4. i/o registers this section gives information on the on- chip i/o register addresses and bit conf iguration. the information is given as shown below. notes on writing to registers are also given at the end. (1) i/o register addresses (address order) ? registers are listed from th e lower allocation addresses. ? registers are classified acco rding to module symbols. ? numbers of cycles for access indicate numbers of cycles of the given base clock. ? among the internal i/o register area, a ddresses not listed in the list of regi sters are reserved. reserved addresses must not be accessed. do not access these addresses; ot herwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. (2) notes on writing to i/o registers when writing to an i/o register , the cpu starts executing the subsequent instru ction before completing i/o register write. this may cause the subsequent instruction to be executed befo re the post-update i/o register value is reflected on the operation. as described in the following examples, sp ecial care is required for the cases in wh ich the subsequent instruction must be executed after the post-update i/o re gister value is actually reflected. [examples of cases requiring special care] ? the subsequent instruction must be execu ted while an interrupt request is disabled with the ienj bit in iern of the icu (interrupt request en able bit) cleared to 0. ? a wait instruction is executed immediately after the preprocessing for causing a transition to the low power consumption state. in the above cases, after writing to an i/o register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) write to an i/o register. (b) read the value from the i/o re gister to a general register. (c) execute the operati on using the value read. (d) execute the subsequent instruction. [instruction examples] ? byte-size i/o registers mov.l #sfr_addr, r1 mov.b #sfr_data, [r1] cmp [r1].ub, r1 ;; next process ? word-size i/o registers mov.l #sfr_addr, r1 mov.w #sfr_data, [r1] cmp [r1].w, r1 ;; next process
r01ds0041ej0150 rev.1.50 page 57 of 221 oct 18, 2013 rx210 group 4. i/o registers ? longword-size i/o registers mov.l #sfr_addr, r1 mov.l #sfr_data, [r1] cmp [r1].l, r1 ;; next process if multiple registers are written to and a subsequent instruc tion should be executed after th e write operati ons are entirely completed, only read the i/o register that was last written to and execute the operation using th e value; it is not necessary to read or execute operation for all the registers that were written to. (3) number of access cycles to i/o registers for numbers of clock cycles fo r access to i/o registers, see table 4.1, list of i/o registers (address order) . the number of access cycles to i/o regist ers is obtained by following equation. * 1 number of access cycles to i/o registers = numb er of bus cycles for internal main bus 1 + number of divided clock synchronization cycles + number of bus cycles for internal peripheral bus 1 to 6 the number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed. when peripheral functions connected to internal peripheral bus 2 to 6 or registers for the ex ternal bus control unit (except for bus error related registers) are accessed, the number of divided clock synchronization cycles is added. the number of divided clock synchronization cycles differs depending on the frequency ratio between iclk and pclk (or fclk, bclk) or bus access timing. in the peripheral function unit, when the fr equency ratio of iclk is equal to or gr eater than that of pclk (or fclk), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of pclk (or fclk) at a maximum. therefore, one pclk (or fclk) has been added to the number of access cycles shown in table 4.1 . when the frequency ratio of iclk is lower than that of pclk (or fclk), the subsequent bus access is started from the iclk cycle following the completion of the access to the peripheral functions. th erefore, the access cycles are described on an iclk basis. in the external bus control unit, the sum of the number of bu s cycles for internal main bus 1 and the number of divided clock synchronization cycles will be one cycle of bclk at a maximum. therefore, one bclk is added to the number of access cycles shown in table 4.1 . note 1. this applies to the number of cycles when the access from th e cpu does not conflict with the instruction fetching to the external memory or bus access from the different bus master (dmac or dtc).
r01ds0041ej0150 rev.1.50 page 58 of 221 oct 18, 2013 rx210 group 4. i/o registers 4.1 i/o register addresses (address order) table 4.1 list of i/o register s (address order) (1 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk 0008 0000h system mode monitor register mdmonr 16 16 3 iclk 0008 0002h system mode status register mdsr 16 16 3 iclk 0008 0006h system system control register 0 syscr0 16 16 3 iclk 0008 0008h system system control register 1 syscr1 16 16 3 iclk 0008 000ch system standby control register sbycr 16 16 3 iclk 0008 0010h system module stop control register a mstpcra 32 32 3 iclk 0008 0014h system module stop control register b mstpcrb 32 32 3 iclk 0008 0018h system module stop control register c mstpcrc 32 32 3 iclk 0008 0020h system system clock control register sckcr 32 32 3 iclk 0008 0026h system system clock control register 3 sckcr3 16 16 3 iclk 0008 0028h system pll control register pllcr 16 16 3 iclk 0008 002ah system pll control register 2 pllcr2 8 8 3 iclk 0008 0030h system external bus clock control register bckcr 8 8 3 iclk 0008 0032h system main clock oscillator control register mosccr 8 8 3 iclk 0008 0033h system sub-clock oscillator control register sosccr 8 8 3 iclk 0008 0034h system low-speed on-chip osc illator control register lococr 8 8 3 iclk 0008 0035h system iwdt-dedicated on-chip oscillator control register ilococr 8 8 3 iclk 0008 0036h system high-speed on-chip oscillator control register hococr 8 8 3 iclk 0008 0037h system high-speed on-chip oscillator control register 2 hococr2 8 8 3 iclk 0008 0040h system oscillation stop detection control register ostdcr 8 8 3 iclk 0008 0041h system oscillation stop detection status register ostdsr 8 8 3 iclk 0008 00a0h system operating power control register opccr 8 8 3 iclk 0008 00a1h system sleep mode return clock source switching register rstckcr 8 8 3 iclk 0008 00a2h system main clock oscillator wait control register moscwtcr 8 8 3 iclk 0008 00a3h system sub-clock oscillator wait control register soscwtcr 8 8 3 iclk 0008 00a6h system pll wait control register pllwtcr 8 8 3 iclk 0008 00a9h system hoco wait control register 2 hocowtcr2 8 8 3 iclk 0008 00c0h system reset status register 2 rstsr2 8 8 3 iclk 0008 00c2h system software reset register swrr 16 16 3 iclk 0008 00e0h system voltage monitoring 1 circuit/comparator a1 control register 1 lvd1cr1 8 8 3 iclk 0008 00e1h system voltage monitoring 1 circuit/comparator a1 status register lvd1sr 8 8 3 iclk 0008 00e2h system voltage monitoring 2 circuit/comparator a2 control register 1 lvd2cr1 8 8 3 iclk 0008 00e3h system voltage monitoring 2 circuit/comparator a2 status register lvd2sr 8 8 3 iclk 0008 0200h system voltage regulator control register vrcr 8 8 3 iclk 0008 03feh system protect register prcr 16 16 3 iclk 0008 1300h bsc bus error status clear register berclr 8 8 2 iclk 0008 1304h bsc bus error monitoring enable register beren 8 8 2 iclk 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk 0008 1310h bsc bus priority control register buspri 16 16 2 iclk 0008 2000h dmac0 dma source address register dmsar 32 32 2 iclk 0008 2004h dmac0 dma destination address register dmdar 32 32 2 iclk 0008 2008h dmac0 dma transfer count register dmcra 32 32 2 iclk 0008 200ch dmac0 dma block transfer count register dmcrb 16 16 2 iclk 0008 2010h dmac0 dma transfer mode register dmtmd 16 16 2 iclk 0008 2013h dmac0 dma interrupt setting register dmint 8 8 2 iclk 0008 2014h dmac0 dma address mode register dmamd 16 16 2 iclk 0008 2018h dmac0 dma offset register dmofr 32 32 2 iclk 0008 201ch dmac0 dma transfer enable register dmcnt 8 8 2 iclk
r01ds0041ej0150 rev.1.50 page 59 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 201dh dmac0 dma software start register dmreq 8 8 2 iclk 0008 201eh dmac0 dma status register dmsts 8 8 2 iclk 0008 201fh dmac0 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2040h dmac1 dma source address register dmsar 32 32 2 iclk 0008 2044h dmac1 dma destination address register dmdar 32 32 2 iclk 0008 2048h dmac1 dma transfer count register dmcra 32 32 2 iclk 0008 204ch dmac1 dma block transfer count register dmcrb 16 16 2 iclk 0008 2050h dmac1 dma transfer mode register dmtmd 16 16 2 iclk 0008 2053h dmac1 dma interrupt setting register dmint 8 8 2 iclk 0008 2054h dmac1 dma address mode register dmamd 16 16 2 iclk 0008 205ch dmac1 dma transfer enable register dmcnt 8 8 2 iclk 0008 205dh dmac1 dma software start register dmreq 8 8 2 iclk 0008 205eh dmac1 dma status register dmsts 8 8 2 iclk 0008 205fh dmac1 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2080h dmac2 dma source address register dmsar 32 32 2 iclk 0008 2084h dmac2 dma destination address register dmdar 32 32 2 iclk 0008 2088h dmac2 dma transfer count register dmcra 32 32 2 iclk 0008 208ch dmac2 dma block transfer count register dmcrb 16 16 2 iclk 0008 2090h dmac2 dma transfer mode register dmtmd 16 16 2 iclk 0008 2093h dmac2 dma interrupt setting register dmint 8 8 2 iclk 0008 2094h dmac2 dma address mode register dmamd 16 16 2 iclk 0008 209ch dmac2 dma transfer enable register dmcnt 8 8 2 iclk 0008 209dh dmac2 dma software start register dmreq 8 8 2 iclk 0008 209eh dmac2 dma status register dmsts 8 8 2 iclk 0008 209fh dmac2 dma activation source flag control register dmcsl 8 8 2 iclk 0008 20c0h dmac3 dma source address register dmsar 32 32 2 iclk 0008 20c4h dmac3 dma destination address register dmdar 32 32 2 iclk 0008 20c8h dmac3 dma transfer count register dmcra 32 32 2 iclk 0008 20cch dmac3 dma block transfer count register dmcrb 16 16 2 iclk 0008 20d0h dmac3 dma transfer mode register dmtmd 16 16 2 iclk 0008 20d3h dmac3 dma interrupt setting register dmint 8 8 2 iclk 0008 20d4h dmac3 dma address mode register dmamd 16 16 2 iclk 0008 20dch dmac3 dma transfer enable register dmcnt 8 8 2 iclk 0008 20ddh dmac3 dma software start register dmreq 8 8 2 iclk 0008 20deh dmac3 dma status register dmsts 8 8 2 iclk 0008 20dfh dmac3 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2200h dmac dma module activation register dmast 8 8 2 iclk 0008 2400h dtc dtc control register dtccr 8 8 2 iclk 0008 2404h dtc dtc vector base register dtcvbr 32 32 2 iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2 iclk 0008 240ch dtc dtc module start register dtcst 8 8 2 iclk 0008 240eh dtc dtc status register dtcsts 16 16 2 iclk 0008 3002h bsc cs0 mode register cs0mod 16 16 1, 2 bclk 0008 3004h bsc cs0 wait control register 1 cs0wcr1 32 32 1, 2 bclk 0008 3008h bsc cs0 wait control register 2 cs0wcr2 32 32 1, 2 bclk 0008 3012h bsc cs1 mode register cs1mod 16 16 1, 2 bclk 0008 3014h bsc cs1 wait control register 1 cs1wcr1 32 32 1, 2 bclk 0008 3018h bsc cs1 wait control register 2 cs1wcr2 32 32 1, 2 bclk 0008 3022h bsc cs2 mode register cs2mod 16 16 1, 2 bclk 0008 3024h bsc cs2 wait control register 1 cs2wcr1 32 32 1, 2 bclk 0008 3028h bsc cs2 wait control register 2 cs2wcr2 32 32 1, 2 bclk table 4.1 list of i/o register s (address order) (2 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 60 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 3032h bsc cs3 mode register cs3mod 16 16 1, 2 bclk 0008 3034h bsc cs3 wait control register 1 cs3wcr1 32 32 1, 2 bclk 0008 3038h bsc cs3 wait control register 2 cs3wcr2 32 32 1, 2 bclk 0008 3802h bsc cs0 control register cs0cr 16 16 1, 2 bclk 0008 380ah bsc cs0 recovery cycle register cs0rec 16 16 1, 2 bclk 0008 3812h bsc cs1 control register cs1cr 16 16 1, 2 bclk 0008 381ah bsc cs1 recovery cycle register cs1rec 16 16 1, 2 bclk 0008 3822h bsc cs2 control register cs2cr 16 16 1, 2 bclk 0008 382ah bsc cs2 recovery cycle register cs2rec 16 16 1, 2 bclk 0008 3832h bsc cs3 control register cs3cr 16 16 1, 2 bclk 0008 383ah bsc cs3 recovery cycle register cs3rec 16 16 1, 2 bclk 0008 3880h bsc cs recovery cycle insertion enable register csrecen 16 16 1, 2 bclk 0008 7010h icu interrupt request register 016 ir016 8 8 2 iclk 0008 7015h icu interrupt request register 021 ir021 8 8 2 iclk 0008 7017h icu interrupt request register 023 ir023 8 8 2 iclk 0008 701bh icu interrupt request register 027 ir027 8 8 2 iclk 0008 701ch icu interrupt request register 028 ir028 8 8 2 iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2 iclk 0008 701eh icu interrupt request register 030 ir030 8 8 2 iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2 iclk 0008 7020h icu interrupt request register 032 ir032 8 8 2 iclk 0008 7021h icu interrupt request register 033 ir033 8 8 2 iclk 0008 7022h icu interrupt request register 034 ir034 8 8 2 iclk 0008 702ch icu interrupt request register 044 ir044 8 8 2 iclk 0008 702dh icu interrupt request register 045 ir045 8 8 2 iclk 0008 702eh icu interrupt request register 046 ir046 8 8 2 iclk 0008 702fh icu interrupt request register 047 ir047 8 8 2 iclk 0008 7039h icu interrupt request register 057 ir057 8 8 2 iclk 0008 703ah icu interrupt request register 058 ir058 8 8 2 iclk 0008 703bh icu interrupt request register 059 ir059 8 8 2 iclk 0008 703fh icu interrupt request register 063 ir063 8 8 2 iclk 0008 7040h icu interrupt request register 064 ir064 8 8 2 iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2 iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2 iclk 0008 7043h icu interrupt request register 067 ir067 8 8 2 iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2 iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2 iclk 0008 7046h icu interrupt request register 070 ir070 8 8 2 iclk 0008 7047h icu interrupt request register 071 ir071 8 8 2 iclk 0008 7058h icu interrupt request register 088 ir088 8 8 2 iclk 0008 7059h icu interrupt request register 089 ir089 8 8 2 iclk 0008 705ch icu interrupt request register 092 ir092 8 8 2 iclk 0008 705dh icu interrupt request register 093 ir093 8 8 2 iclk 0008 7066h icu interrupt request register 102 ir102 8 8 2 iclk 0008 7067h icu interrupt request register 103 ir103 8 8 2 iclk 0008 706ah icu interrupt request register 106 ir106 8 8 2 iclk 0008 706bh icu interrupt request register 107 ir107 8 8 2 iclk 0008 7072h icu interrupt request register 114 ir114 8 8 2 iclk 0008 7073h icu interrupt request register 115 ir115 8 8 2 iclk 0008 7074h icu interrupt request register 116 ir116 8 8 2 iclk 0008 7075h icu interrupt request register 117 ir117 8 8 2 iclk table 4.1 list of i/o register s (address order) (3 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 61 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 7076h icu interrupt request register 118 ir118 8 8 2 iclk 0008 7077h icu interrupt request register 119 ir119 8 8 2 iclk 0008 7078h icu interrupt request register 120 ir120 8 8 2 iclk 0008 7079h icu interrupt request register 121 ir121 8 8 2 iclk 0008 707ah icu interrupt request register 122 ir122 8 8 2 iclk 0008 707bh icu interrupt request register 123 ir123 8 8 2 iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2 iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2 iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2 iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2 iclk 0008 7080h icu interrupt request register 128 ir128 8 8 2 iclk 0008 7081h icu interrupt request register 129 ir129 8 8 2 iclk 0008 7082h icu interrupt request register 130 ir130 8 8 2 iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2 iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2 iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2 iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2 iclk 0008 7087h icu interrupt request register 135 ir135 8 8 2 iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2 iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2 iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2 iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2 iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2 iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2 iclk 0008 708eh icu interrupt request register 142 ir142 8 8 2 iclk 0008 708fh icu interrupt request register 143 ir143 8 8 2 iclk 0008 7090h icu interrupt request register 144 ir144 8 8 2 iclk 0008 7091h icu interrupt request register 145 ir145 8 8 2 iclk 0008 7092h icu interrupt request register 146 ir146 8 8 2 iclk 0008 7093h icu interrupt request register 147 ir147 8 8 2 iclk 0008 7094h icu interrupt request register 148 ir148 8 8 2 iclk 0008 7095h icu interrupt request register 149 ir149 8 8 2 iclk 0008 7096h icu interrupt request register 150 ir150 8 8 2 iclk 0008 7097h icu interrupt request register 151 ir151 8 8 2 iclk 0008 7098h icu interrupt request register 152 ir152 8 8 2 iclk 0008 7099h icu interrupt request register 153 ir153 8 8 2 iclk 0008 709ah icu interrupt request register 154 ir154 8 8 2 iclk 0008 709bh icu interrupt request register 155 ir155 8 8 2 iclk 0008 709ch icu interrupt request register 156 ir156 8 8 2 iclk 0008 709dh icu interrupt request register 157 ir157 8 8 2 iclk 0008 709eh icu interrupt request register 158 ir158 8 8 2 iclk 0008 709fh icu interrupt request register 159 ir159 8 8 2 iclk 0008 70a0h icu interrupt request register 160 ir160 8 8 2 iclk 0008 70a1h icu interrupt request register 161 ir161 8 8 2 iclk 0008 70a2h icu interrupt request register 162 ir162 8 8 2 iclk 0008 70a3h icu interrupt request register 163 ir163 8 8 2 iclk 0008 70a4h icu interrupt request register 164 ir164 8 8 2 iclk 0008 70a5h icu interrupt request register 165 ir165 8 8 2 iclk 0008 70a6h icu interrupt request register 166 ir166 8 8 2 iclk 0008 70a7h icu interrupt request register 167 ir167 8 8 2 iclk 0008 70aah icu interrupt request register 170 ir170 8 8 2 iclk table 4.1 list of i/o register s (address order) (4 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 62 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 70abh icu interrupt request register 171 ir171 8 8 2 iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2 iclk 0008 70afh icu interrupt request register 175 ir175 8 8 2 iclk 0008 70b0h icu interrupt request register 176 ir176 8 8 2 iclk 0008 70b1h icu interrupt request register 177 ir177 8 8 2 iclk 0008 70b2h icu interrupt request register 178 ir178 8 8 2 iclk 0008 70b3h icu interrupt request register 179 ir179 8 8 2 iclk 0008 70b4h icu interrupt request register 180 ir180 8 8 2 iclk 0008 70b5h icu interrupt request register 181 ir181 8 8 2 iclk 0008 70b6h icu interrupt request register 182 ir182 8 8 2 iclk 0008 70b7h icu interrupt request register 183 ir183 8 8 2 iclk 0008 70b8h icu interrupt request register 184 ir184 8 8 2 iclk 0008 70b9h icu interrupt request register 185 ir185 8 8 2 iclk 0008 70bah icu interrupt request register 186 ir186 8 8 2 iclk 0008 70bbh icu interrupt request register 187 ir187 8 8 2 iclk 0008 70bch icu interrupt request register 188 ir188 8 8 2 iclk 0008 70bdh icu interrupt request register 189 ir189 8 8 2 iclk 0008 70beh icu interrupt request register 190 ir190 8 8 2 iclk 0008 70bfh icu interrupt request register 191 ir191 8 8 2 iclk 0008 70c0h icu interrupt request register 192 ir192 8 8 2 iclk 0008 70c1h icu interrupt request register 193 ir193 8 8 2 iclk 0008 70c2h icu interrupt request register 194 ir194 8 8 2 iclk 0008 70c3h icu interrupt request register 195 ir195 8 8 2 iclk 0008 70c4h icu interrupt request register 196 ir196 8 8 2 iclk 0008 70c5h icu interrupt request register 197 ir197 8 8 2 iclk 0008 70c6h icu interrupt request register 198 ir198 8 8 2 iclk 0008 70c7h icu interrupt request register 199 ir199 8 8 2 iclk 0008 70c8h icu interrupt request register 200 ir200 8 8 2 iclk 0008 70c9h icu interrupt request register 201 ir201 8 8 2 iclk 0008 70ceh icu interrupt request register 206 ir206 8 8 2 iclk 0008 70cfh icu interrupt request register 207 ir207 8 8 2 iclk 0008 70d0h icu interrupt request register 208 ir208 8 8 2 iclk 0008 70d1h icu interrupt request register 209 ir209 8 8 2 iclk 0008 70d2h icu interrupt request register 210 ir210 8 8 2 iclk 0008 70d3h icu interrupt request register 211 ir211 8 8 2 iclk 0008 70d4h icu interrupt request register 212 ir212 8 8 2 iclk 0008 70d5h icu interrupt request register 213 ir213 8 8 2 iclk 0008 70d6h icu interrupt request register 214 ir214 8 8 2 iclk 0008 70d7h icu interrupt request register 215 ir215 8 8 2 iclk 0008 70d8h icu interrupt request register 216 ir216 8 8 2 iclk 0008 70d9h icu interrupt request register 217 ir217 8 8 2 iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2 iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2 iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2 iclk 0008 70ddh icu interrupt request register 221 ir221 8 8 2 iclk 0008 70deh icu interrupt request register 222 ir222 8 8 2 iclk 0008 70dfh icu interrupt request register 223 ir223 8 8 2 iclk 0008 70e0h icu interrupt request register 224 ir224 8 8 2 iclk 0008 70e1h icu interrupt request register 225 ir225 8 8 2 iclk 0008 70e2h icu interrupt request register 226 ir226 8 8 2 iclk 0008 70e3h icu interrupt request register 227 ir227 8 8 2 iclk table 4.1 list of i/o register s (address order) (5 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 63 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 70e4h icu interrupt request register 228 ir228 8 8 2 iclk 0008 70e5h icu interrupt request register 229 ir229 8 8 2 iclk 0008 70e6h icu interrupt request register 230 ir230 8 8 2 iclk 0008 70e7h icu interrupt request register 231 ir231 8 8 2 iclk 0008 70e8h icu interrupt request register 232 ir232 8 8 2 iclk 0008 70e9h icu interrupt request register 233 ir233 8 8 2 iclk 0008 70eah icu interrupt request register 234 ir234 8 8 2 iclk 0008 70ebh icu interrupt request register 235 ir235 8 8 2 iclk 0008 70ech icu interrupt request register 236 ir236 8 8 2 iclk 0008 70edh icu interrupt request register 237 ir237 8 8 2 iclk 0008 70eeh icu interrupt request register 238 ir238 8 8 2 iclk 0008 70efh icu interrupt request register 239 ir239 8 8 2 iclk 0008 70f0h icu interrupt request register 240 ir240 8 8 2 iclk 0008 70f1h icu interrupt request register 241 ir241 8 8 2 iclk 0008 70f2h icu interrupt request register 242 ir242 8 8 2 iclk 0008 70f3h icu interrupt request register 243 ir243 8 8 2 iclk 0008 70f4h icu interrupt request register 244 ir244 8 8 2 iclk 0008 70f5h icu interrupt request register 245 ir245 8 8 2 iclk 0008 70f6h icu interrupt request register 246 ir246 8 8 2 iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2 iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2 iclk 0008 70f9h icu interrupt request register 249 ir249 8 8 2 iclk 0008 70fah icu interrupt request register 250 ir250 8 8 2 iclk 0008 70fbh icu interrupt request register 251 ir251 8 8 2 iclk 0008 70fch icu interrupt request register 252 ir252 8 8 2 iclk 0008 70fdh icu interrupt request register 253 ir253 8 8 2 iclk 0008 711bh icu dtc activation enable register 027 dtcer027 8 8 2 iclk 0008 711ch icu dtc activation enable register 028 dtcer028 8 8 2 iclk 0008 711dh icu dtc activation enable register 029 dtcer029 8 8 2 iclk 0008 711eh icu dtc activation enable register 030 dtcer030 8 8 2 iclk 0008 711fh icu dtc activation enable register 031 dtcer031 8 8 2 iclk 0008 712dh icu dtc activation enable register 045 dtcer045 8 8 2 iclk 0008 712eh icu dtc activation enable register 046 dtcer046 8 8 2 iclk 0008 713ah icu dtc activation enable register 058 dtcer058 8 8 2 iclk 0008 713bh icu dtc activation enable register 059 dtcer059 8 8 2 iclk 0008 7140h icu dtc activation enable register 064 dtcer064 8 8 2 iclk 0008 7141h icu dtc activation enable register 065 dtcer065 8 8 2 iclk 0008 7142h icu dtc activation enable register 066 dtcer066 8 8 2 iclk 0008 7143h icu dtc activation enable register 067 dtcer067 8 8 2 iclk 0008 7144h icu dtc activation enable register 068 dtcer068 8 8 2 iclk 0008 7145h icu dtc activation enable register 069 dtcer069 8 8 2 iclk 0008 7146h icu dtc activation enable register 070 dtcer070 8 8 2 iclk 0008 7147h icu dtc activation enable register 071 dtcer071 8 8 2 iclk 0008 7166h icu dtc activation enable register 102 dtcer102 8 8 2 iclk 0008 7167h icu dtc activation enable register 103 dtcer103 8 8 2 iclk 0008 716ah icu dtc activation enable register 106 dtcer106 8 8 2 iclk 0008 716bh icu dtc activation enable register 107 dtcer107 8 8 2 iclk 0008 7172h icu dtc activation enable register 114 dtcer114 8 8 2 iclk 0008 7173h icu dtc activation enable register 115 dtcer115 8 8 2 iclk 0008 7174h icu dtc activation enable register 116 dtcer116 8 8 2 iclk 0008 7175h icu dtc activation enable register 117 dtcer117 8 8 2 iclk table 4.1 list of i/o register s (address order) (6 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 64 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 7179h icu dtc activation enable register 121 dtcer121 8 8 2 iclk 0008 717ah icu dtc activation enable register 122 dtcer122 8 8 2 iclk 0008 717dh icu dtc activation enable register 125 dtcer125 8 8 2 iclk 0008 717eh icu dtc activation enable register 126 dtcer126 8 8 2 iclk 0008 7181h icu dtc activation enable register 129 dtcer129 8 8 2 iclk 0008 7182h icu dtc activation enable register 130 dtcer130 8 8 2 iclk 0008 7183h icu dtc activation enable register 131 dtcer131 8 8 2 iclk 0008 7184h icu dtc activation enable register 132 dtcer132 8 8 2 iclk 0008 7186h icu dtc activation enable register 134 dtcer134 8 8 2 iclk 0008 7187h icu dtc activation enable register 135 dtcer135 8 8 2 iclk 0008 7188h icu dtc activation enable register 136 dtcer136 8 8 2 iclk 0008 7189h icu dtc activation enable register 137 dtcer137 8 8 2 iclk 0008 718ah icu dtc activation enable register 138 dtcer138 8 8 2 iclk 0008 718bh icu dtc activation enable register 139 dtcer139 8 8 2 iclk 0008 718ch icu dtc activation enable register 140 dtcer140 8 8 2 iclk 0008 718dh icu dtc activation enable register 141 dtcer141 8 8 2 iclk 0008 718eh icu dtc activation enable register 142 dtcer142 8 8 2 iclk 0008 718fh icu dtc activation enable register 143 dtcer143 8 8 2 iclk 0008 7190h icu dtc activation enable register 144 dtcer144 8 8 2 iclk 0008 7191h icu dtc activation enable register 145 dtcer145 8 8 2 iclk 0008 7193h icu dtc activation enable register 147 dtcer147 8 8 2 iclk 0008 7194h icu dtc activation enable register 148 dtcer148 8 8 2 iclk 0008 7197h icu dtc activation enable register 151 dtcer151 8 8 2 iclk 0008 7198h icu dtc activation enable register 152 dtcer152 8 8 2 iclk 0008 719bh icu dtc activation enable register 155 dtcer155 8 8 2 iclk 0008 719ch icu dtc activation enable register 156 dtcer156 8 8 2 iclk 0008 719dh icu dtc activation enable register 157 dtcer157 8 8 2 iclk 0008 719eh icu dtc activation enable register 158 dtcer158 8 8 2 iclk 0008 71a0h icu dtc activation enable register 160 dtcer160 8 8 2 iclk 0008 71a1h icu dtc activation enable register 161 dtcer161 8 8 2 iclk 0008 71a4h icu dtc activation enable register 164 dtcer164 8 8 2 iclk 0008 71a5h icu dtc activation enable register 165 dtcer165 8 8 2 iclk 0008 71aeh icu dtc activation enable register 174 dtcer174 8 8 2 iclk 0008 71afh icu dtc activation enable register 175 dtcer175 8 8 2 iclk 0008 71b1h icu dtc activation enable register 177 dtcer177 8 8 2 iclk 0008 71b2h icu dtc activation enable register 178 dtcer178 8 8 2 iclk 0008 71b4h icu dtc activation enable register 180 dtcer180 8 8 2 iclk 0008 71b5h icu dtc activation enable register 181 dtcer181 8 8 2 iclk 0008 71b7h icu dtc activation enable register 183 dtcer183 8 8 2 iclk 0008 71b8h icu dtc activation enable register 184 dtcer184 8 8 2 iclk 0008 71bbh icu dtc activation enable register 187 dtcer187 8 8 2 iclk 0008 71bch icu dtc activation enable register 188 dtcer188 8 8 2 iclk 0008 71bfh icu dtc activation enable register 191 dtcer191 8 8 2 iclk 0008 71c0h icu dtc activation enable register 192 dtcer192 8 8 2 iclk 0008 71c3h icu dtc activation enable register 195 dtcer195 8 8 2 iclk 0008 71c4h icu dtc activation enable register 196 dtcer196 8 8 2 iclk 0008 71c6h icu dtc activation enable register 198 dtcer198 8 8 2 iclk 0008 71c7h icu dtc activation enable register 199 dtcer199 8 8 2 iclk 0008 71c8h icu dtc activation enable register 200 dtcer200 8 8 2 iclk 0008 71c9h icu dtc activation enable register 201 dtcer201 8 8 2 iclk 0008 71cfh icu dtc activation enable register 207 dtcer207 8 8 2 iclk table 4.1 list of i/o register s (address order) (7 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 65 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 71d0h icu dtc activation enable register 208 dtcer208 8 8 2 iclk 0008 71d3h icu dtc activation enable register 211 dtcer211 8 8 2 iclk 0008 71d4h icu dtc activation enable register 212 dtcer212 8 8 2 iclk 0008 71d7h icu dtc activation enable register 215 dtcer215 8 8 2 iclk 0008 71d8h icu dtc activation enable register 216 dtcer216 8 8 2 iclk 0008 71dbh icu dtc activation enable register 219 dtcer219 8 8 2 iclk 0008 71dch icu dtc activation enable register 220 dtcer220 8 8 2 iclk 0008 71dfh icu dtc activation enable register 223 dtcer223 8 8 2 iclk 0008 71e0h icu dtc activation enable register 224 dtcer224 8 8 2 iclk 0008 71e3h icu dtc activation enable register 227 dtcer227 8 8 2 iclk 0008 71e4h icu dtc activation enable register 228 dtcer228 8 8 2 iclk 0008 71e7h icu dtc activation enable register 231 dtcer231 8 8 2 iclk 0008 71e8h icu dtc activation enable register 232 dtcer232 8 8 2 iclk 0008 71ebh icu dtc activation enable register 235 dtcer235 8 8 2 iclk 0008 71ech icu dtc activation enable register 236 dtcer236 8 8 2 iclk 0008 71efh icu dtc activation enable register 239 dtcer239 8 8 2 iclk 0008 71f0h icu dtc activation enable register 240 dtcer240 8 8 2 iclk 0008 71f7h icu dtc activation enable register 247 dtcer247 8 8 2 iclk 0008 71f8h icu dtc activation enable register 248 dtcer248 8 8 2 iclk 0008 71fbh icu dtc activation enable register 251 dtcer251 8 8 2 iclk 0008 71fch icu dtc activation enable register 252 dtcer252 8 8 2 iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2 iclk 0008 7203h icu interrupt request enable register 03 ier03 8 8 2 iclk 0008 7204h icu interrupt request enable register 04 ier04 8 8 2 iclk 0008 7205h icu interrupt request enable register 05 ier05 8 8 2 iclk 0008 7207h icu interrupt request enable register 07 ier07 8 8 2 iclk 0008 7208h icu interrupt request enable register 08 ier08 8 8 2 iclk 0008 720bh icu interrupt request enable register 0b ier0b 8 8 2 iclk 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2 iclk 0008 720dh icu interrupt request enable register 0d ier0d 8 8 2 iclk 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2 iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2 iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2 iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2 iclk 0008 7212h icu interrupt request enable register 12 ier12 8 8 2 iclk 0008 7213h icu interrupt request enable register 13 ier13 8 8 2 iclk 0008 7214h icu interrupt request enable register 14 ier14 8 8 2 iclk 0008 7215h icu interrupt request enable register 15 ier15 8 8 2 iclk 0008 7216h icu interrupt request enable register 16 ier16 8 8 2 iclk 0008 7217h icu interrupt request enable register 17 ier17 8 8 2 iclk 0008 7218h icu interrupt request enable register 18 ier18 8 8 2 iclk 0008 7219h icu interrupt request enable register 19 ier19 8 8 2 iclk 0008 721ah icu interrupt request enable register 1a ier1a 8 8 2 iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2 iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2 iclk 0008 721dh icu interrupt request enable register 1d ier1d 8 8 2 iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2 iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2 iclk 0008 72e0h icu software interrupt activation register swintr 8 8 2 iclk 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk 0008 7300h icu interrupt source priority register 000 ipr000 8 8 2 iclk table 4.1 list of i/o register s (address order) (8 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 66 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 7301h icu interrupt source priority register 001 ipr001 8 8 2 iclk 0008 7302h icu interrupt source priority register 002 ipr002 8 8 2 iclk 0008 7303h icu interrupt source priority register 003 ipr003 8 8 2 iclk 0008 7304h icu interrupt source priority register 004 ipr004 8 8 2 iclk 0008 7305h icu interrupt source priority register 005 ipr005 8 8 2 iclk 0008 7306h icu interrupt source priority register 006 ipr006 8 8 2 iclk 0008 7307h icu interrupt source priority register 007 ipr007 8 8 2 iclk 0008 7320h icu interrupt source priority register 032 ipr032 8 8 2 iclk 0008 7321h icu interrupt source priority register 033 ipr033 8 8 2 iclk 0008 7322h icu interrupt source priority register 034 ipr034 8 8 2 iclk 0008 732ch icu interrupt source priority register 044 ipr044 8 8 2 iclk 0008 7339h icu interrupt source priority register 057 ipr057 8 8 2 iclk 0008 733ah icu interrupt source priority register 058 ipr058 8 8 2 iclk 0008 733bh icu interrupt source priority register 059 ipr059 8 8 2 iclk 0008 733fh icu interrupt source priority register 063 ipr063 8 8 2 iclk 0008 7340h icu interrupt source priority register 064 ipr064 8 8 2 iclk 0008 7341h icu interrupt source priority register 065 ipr065 8 8 2 iclk 0008 7342h icu interrupt source priority register 066 ipr066 8 8 2 iclk 0008 7343h icu interrupt source priority register 067 ipr067 8 8 2 iclk 0008 7344h icu interrupt source priority register 068 ipr068 8 8 2 iclk 0008 7345h icu interrupt source priority register 069 ipr069 8 8 2 iclk 0008 7346h icu interrupt source priority register 070 ipr070 8 8 2 iclk 0008 7347h icu interrupt source priority register 071 ipr071 8 8 2 iclk 0008 7358h icu interrupt source priority register 088 ipr088 8 8 2 iclk 0008 7359h icu interrupt source priority register 089 ipr089 8 8 2 iclk 0008 735ch icu interrupt source priority register 092 ipr092 8 8 2 iclk 0008 735dh icu interrupt source priority register 093 ipr093 8 8 2 iclk 0008 7366h icu interrupt source priority register 102 ipr102 8 8 2 iclk 0008 7367h icu interrupt source priority register 103 ipr103 8 8 2 iclk 0008 736ah icu interrupt source priority register 106 ipr106 8 8 2 iclk 0008 736bh icu interrupt source priority register 107 ipr107 8 8 2 iclk 0008 7372h icu interrupt source priority register 114 ipr114 8 8 2 iclk 0008 7376h icu interrupt source priority register 118 ipr118 8 8 2 iclk 0008 7379h icu interrupt source priority register 121 ipr121 8 8 2 iclk 0008 737bh icu interrupt source priority register 123 ipr123 8 8 2 iclk 0008 737dh icu interrupt source priority register 125 ipr125 8 8 2 iclk 0008 737fh icu interrupt source priority register 127 ipr127 8 8 2 iclk 0008 7381h icu interrupt source priority register 129 ipr129 8 8 2 iclk 0008 7385h icu interrupt source priority register 133 ipr133 8 8 2 iclk 0008 7386h icu interrupt source priority register 134 ipr134 8 8 2 iclk 0008 738ah icu interrupt source priority register 138 ipr138 8 8 2 iclk 0008 738bh icu interrupt source priority register 139 ipr139 8 8 2 iclk 0008 738eh icu interrupt source priority register 142 ipr142 8 8 2 iclk 0008 7392h icu interrupt source priority register 146 ipr146 8 8 2 iclk 0008 7393h icu interrupt source priority register 147 ipr147 8 8 2 iclk 0008 7395h icu interrupt source priority register 149 ipr149 8 8 2 iclk 0008 7397h icu interrupt source priority register 151 ipr151 8 8 2 iclk 0008 7399h icu interrupt source priority register 153 ipr153 8 8 2 iclk 0008 739bh icu interrupt source priority register 155 ipr155 8 8 2 iclk 0008 739fh icu interrupt source priority register 159 ipr159 8 8 2 iclk 0008 73a0h icu interrupt source priority register 160 ipr160 8 8 2 iclk table 4.1 list of i/o register s (address order) (9 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 67 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 738a2 icu interrupt source priority register 162 ipr162 8 8 2 iclk 0008 73a4h icu interrupt source priority register 164 ipr164 8 8 2 iclk 0008 73a6h icu interrupt source priority register 166 ipr166 8 8 2 iclk 0008 73aah icu interrupt source priority register 170 ipr170 8 8 2 iclk 0008 73abh icu interrupt source priority register 171 ipr171 8 8 2 iclk 0008 73aeh icu interrupt source priority register 174 ipr174 8 8 2 iclk 0008 73b1h icu interrupt source priority register 177 ipr177 8 8 2 iclk 0008 73b4h icu interrupt source priority register 180 ipr180 8 8 2 iclk 0008 73b7h icu interrupt source priority register 183 ipr183 8 8 2 iclk 0008 73bah icu interrupt source priority register 186 ipr186 8 8 2 iclk 0008 73beh icu interrupt source priority register 190 ipr190 8 8 2 iclk 0008 73c2h icu interrupt source priority register 194 ipr194 8 8 2 iclk 0008 73c6h icu interrupt source priority register 198 ipr198 8 8 2 iclk 0008 73c7h icu interrupt source priority register 199 ipr199 8 8 2 iclk 0008 73c8h icu interrupt source priority register 200 ipr200 8 8 2 iclk 0008 73c9h icu interrupt source priority register 201 ipr201 8 8 2 iclk 0008 73ceh icu interrupt source priority register 206 ipr206 8 8 2 iclk 0008 73d2h icu interrupt source priority register 210 ipr210 8 8 2 iclk 0008 73d6h icu interrupt source priority register 214 ipr214 8 8 2 iclk 0008 73dah icu interrupt source priority register 218 ipr218 8 8 2 iclk 0008 73deh icu interrupt source priority register 222 ipr222 8 8 2 iclk 0008 73e2h icu interrupt source priority register 226 ipr226 8 8 2 iclk 0008 73e6h icu interrupt source priority register 230 ipr230 8 8 2 iclk 0008 73eah icu interrupt source priority register 234 ipr234 8 8 2 iclk 0008 73eeh icu interrupt source priority register 238 ipr238 8 8 2 iclk 0008 73f2h icu interrupt source priority register 242 ipr242 8 8 2 iclk 0008 73f3h icu interrupt source priority register 243 ipr243 8 8 2 iclk 0008 73f4h icu interrupt source priority register 244 ipr244 8 8 2 iclk 0008 73f5h icu interrupt source priority register 245 ipr245 8 8 2 iclk 0008 73f6h icu interrupt source priority register 246 ipr246 8 8 2 iclk 0008 73f7h icu interrupt source priority register 247 ipr247 8 8 2 iclk 0008 73f8h icu interrupt source priority register 248 ipr248 8 8 2 iclk 0008 73f9h icu interrupt source priority register 249 ipr249 8 8 2 iclk 0008 73fah icu interrupt source priority register 250 ipr250 8 8 2 iclk 0008 7400h icu dmac activation request select register 0 dmrsr0 8 8 2 iclk 0008 7404h icu dmac activation request select register 1 dmrsr1 8 8 2 iclk 0008 7408h icu dmac activation request select register 2 dmrsr2 8 8 2 iclk 0008 740ch icu dmac activation request select register 3 dmrsr3 8 8 2 iclk 0008 7500h icu irq control register 0 irqcr0 8 8 2 iclk 0008 7501h icu irq control register 1 irqcr1 8 8 2 iclk 0008 7502h icu irq control register 2 irqcr2 8 8 2 iclk 0008 7503h icu irq control register 3 irqcr3 8 8 2 iclk 0008 7504h icu irq control register 4 irqcr4 8 8 2 iclk 0008 7505h icu irq control register 5 irqcr5 8 8 2 iclk 0008 7506h icu irq control register 6 irqcr6 8 8 2 iclk 0008 7507h icu irq control register 7 irqcr7 8 8 2 iclk 0008 7510h icu irq pin digital filter enable register 0 irqflte0 8 8 2 iclk 0008 7514h icu irq pin digital filter setting register 0 irqfltc0 16 16 2 iclk 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 iclk 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 iclk 0008 7582h icu non-maskable interrupt clear register nmiclr 8 8 2 iclk table 4.1 list of i/o register s (address order) (10 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 68 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk 0008 7590h icu nmi pin digital filter enable register nmiflte 8 8 2 iclk 0008 7594h icu nmi pin digital filter setting register nmifltc 8 8 2 iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2, 3 pclkb 2 iclk 0008 8002h cmt0 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 8004h cmt0 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 8006h cmt0 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8008h cmt1 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 800ah cmt1 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 800ch cmt1 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8010h cmt compare match timer start register 1 cmstr1 16 16 2, 3 pclkb 2 iclk 0008 8012h cmt2 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 8014h cmt2 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 8016h cmt2 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8018h cmt3 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 801ah cmt3 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 801ch cmt3 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8020h wdt wdt refresh register wdtrr 8 8 2, 3 pclkb 2 iclk 0008 8022h wdt wdt control register wdtcr 16 16 2, 3 pclkb 2 iclk 0008 8024h wdt wdt status register wdtsr 16 16 2, 3 pclkb 2 iclk 0008 8026h wdt wdt reset control register wdtrcr 8 8 2, 3 pclkb 2 iclk 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2, 3 pclkb 2 iclk 0008 8032h iwdt iwdt control register iwdtcr 16 16 2, 3 pclkb 2 iclk 0008 8034h iwdt iwdt status register iwdtsr 16 16 2, 3 pclkb 2 iclk 0008 8036h iwdt iwdt reset control register iwdtrcr 8 8 2, 3 pclkb 2 iclk 0008 8038h iwdt iwdt count stop control register iwdtcstpr 8 8 2, 3 pclkb 2 iclk 0008 80c0h da d/a data register 0 dadr0 16 16 2, 3 pclkb 2 iclk 0008 80c2h da d/a data register 1 dadr1 16 16 2, 3 pclkb 2 iclk 0008 80c4h da d/a control register dacr 8 8 2, 3 pclkb 2 iclk 0008 80c5h da dadrm format select register dadpr 8 8 2, 3 pclkb 2 iclk 0008 8100h tpu timer start register tstr 8 8 2, 3 pclkb 2 iclk 0008 8101h tpu timer synchronous register tsyr 8 8 2, 3 pclkb 2 iclk 0008 8108h tpu0 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk 0008 8109h tpu1 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk 0008 810ah tpu2 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk 0008 810bh tpu3 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk 0008 810ch tpu4 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk 0008 810dh tpu5 noise filter control register nfcr 8 8 2, 3 pclkb 2 iclk 0008 8110h tpu0 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8111h tpu0 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8112h tpu0 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk 0008 8113h tpu0 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk 0008 8114h tpu0 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8115h tpu0 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8116h tpu0 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8118h tpu0 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 811ah tpu0 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 811ch tpu0 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk 0008 811eh tpu0 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk 0008 8120h tpu1 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8121h tpu1 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (11 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 69 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 8122h tpu1 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk 0008 8124h tpu1 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8125h tpu1 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8126h tpu1 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8128h tpu1 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 812ah tpu1 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8130h tpu2 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8131h tpu2 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8132h tpu2 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk 0008 8134h tpu2 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8135h tpu2 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8136h tpu2 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8138h tpu2 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 813ah tpu2 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8140h tpu3 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8141h tpu3 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8142h tpu3 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk 0008 8143h tpu3 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk 0008 8144h tpu3 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8145h tpu3 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8146h tpu3 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8148h tpu3 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 814ah tpu3 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 814ch tpu3 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk 0008 814eh tpu3 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk 0008 8150h tpu4 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8151h tpu4 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8152h tpu4 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk 0008 8154h tpu4 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8155h tpu4 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8156h tpu4 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8158h tpu4 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 815ah tpu4 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8160h tpu5 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8161h tpu5 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8162h tpu5 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk 0008 8164h tpu5 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8165h tpu5 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8166h tpu5 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8168h tpu5 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 816ah tpu5 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8200h tmr0 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8201h tmr1 timer counter control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8202h tmr0 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk 0008 8203h tmr1 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk 0008 8204h tmr0 time constant register a tcora 8 8 2, 3 pclkb 2 iclk 0008 8205h tmr1 time constant register a tcora 8 8* 1 2, 3 pclkb 2 iclk 0008 8206h tmr0 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk 0008 8207h tmr1 time constant register b tcorb 8 8* 1 2, 3 pclkb 2 iclk 0008 8208h tmr0 timer counter tcnt 8 8 2, 3 pclkb 2 iclk 0008 8209h tmr1 timer counter tcnt 8 8* 1 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (12 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 70 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 820ah tmr0 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk 0008 820bh tmr1 timer counter control register tccr 8 8* 1 2, 3 pclkb 2 iclk 0008 820ch tmr0 time count start register tcstr 8 8 2, 3 pclkb 2 iclk 0008 8210h tmr2 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8211h tmr3 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8212h tmr2 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk 0008 8213h tmr3 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk 0008 8214h tmr2 time constant register a tcora 8 8 2, 3 pclkb 2 iclk 0008 8215h tmr3 time constant register a tcora 8 8* 1 2, 3 pclkb 2 iclk 0008 8216h tmr2 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk 0008 8217h tmr3 time constant register b tcorb 8 8* 1 2, 3 pclkb 2 iclk 0008 8218h tmr2 timer counter tcnt 8 8 2, 3 pclkb 2 iclk 0008 8219h tmr3 timer counter tcnt 8 8* 1 2, 3 pclkb 2 iclk 0008 821ah tmr2 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk 0008 821bh tmr3 timer counter control register tccr 8 8* 1 2, 3 pclkb 2 iclk 0008 821ch tmr2 time count start register tcstr 8 8 2, 3 pclkb 2 iclk 0008 8280h crc crc control register crccr 8 8 2, 3 pclkb 2 iclk 0008 8281h crc crc data input register crcdir 8 8 2, 3 pclkb 2 iclk 0008 8282h crc crc data output register crcdor 16 16 2, 3 pclkb 2 iclk 0008 8300h riic0 i 2 c bus control register 1 iccr1 8 8 2, 3 pclkb 2 iclk 0008 8301h riic0 i 2 c bus control register 2 iccr2 8 8 2, 3 pclkb 2 iclk 0008 8302h riic0 i 2 c bus mode register 1 icmr1 8 8 2, 3 pclkb 2 iclk 0008 8303h riic0 i 2 c bus mode register 2 icmr2 8 8 2, 3 pclkb 2 iclk 0008 8304h riic0 i 2 c bus mode register 3 icmr3 8 8 2, 3 pclkb 2 iclk 0008 8305h riic0 i 2 c bus function enable register icfer 8 8 2, 3 pclkb 2 iclk 0008 8306h riic0 i 2 c bus status enable register icser 8 8 2, 3 pclkb 2 iclk 0008 8307h riic0 i 2 c bus interrupt enable register icier 8 8 2, 3 pclkb 2 iclk 0008 8308h riic0 i 2 c bus status register 1 icsr1 8 8 2, 3 pclkb 2 iclk 0008 8309h riic0 i 2 c bus status register 2 icsr2 8 8 2, 3 pclkb 2 iclk 0008 830ah riic0 slave address register l0 sarl0 8 8 2, 3 pclkb 2 iclk 0008 830ah riic0 timeout internal counter l tmocntl 8 8 2, 3 pclkb 2 iclk 0008 830bh riic0 slave address register u0 saru0 8 8 2, 3 pclkb 2 iclk 0008 830bh riic0 timeout internal counter u tmocntu 8 8* 2 2, 3 pclkb 2 iclk 0008 830ch riic0 slave address register l1 sarl1 8 8 2, 3 pclkb 2 iclk 0008 830dh riic0 slave address register u1 saru1 8 8 2, 3 pclkb 2 iclk 0008 830eh riic0 slave address register l2 sarl2 8 8 2, 3 pclkb 2 iclk 0008 830fh riic0 slave address register u2 saru2 8 8 2, 3 pclkb 2 iclk 0008 8310h riic0 i 2 c bus bit rate low-level register icbrl 8 8 2, 3 pclkb 2 iclk 0008 8311h riic0 i 2 c bus bit rate high-level register icbrh 8 8 2, 3 pclkb 2 iclk 0008 8312h riic0 i 2 c bus transmit data register icdrt 8 8 2, 3 pclkb 2 iclk 0008 8313h riic0 i 2 c bus receive data register icdrr 8 8 2, 3 pclkb 2 iclk 0008 8380h rspi0 rspi control register spcr 8 8 2, 3 pclkb 2 iclk 0008 8381h rspi0 rspi slave select polarity register sslp 8 8 2, 3 pclkb 2 iclk 0008 8382h rspi0 rspi pin control register sppcr 8 8 2, 3 pclkb 2 iclk 0008 8383h rspi0 rspi status register spsr 8 8 2, 3 pclkb 2 iclk 0008 8384h rspi0 rspi data register spdr 32 16, 32 2, 3 pclkb 2 iclk 0008 8388h rspi0 rspi sequence control register spscr 8 8 2, 3 pclkb 2 iclk 0008 8389h rspi0 rspi sequence status register spssr 8 8 2, 3 pclkb 2 iclk 0008 838ah rspi0 rspi bit rate register spbr 8 8 2, 3 pclkb 2 iclk 0008 838bh rspi0 rspi data control register spdcr 8 8 2, 3 pclkb 2 iclk 0008 838ch rspi0 rspi clock delay register spckd 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (13 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 71 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 838dh rspi0 rspi slave select negation delay register sslnd 8 8 2, 3 pclkb 2 iclk 0008 838eh rspi0 rspi next-access delay register spnd 8 8 2, 3 pclkb 2 iclk 0008 838fh rspi0 rspi control register 2 spcr2 8 8 2, 3 pclkb 2 iclk 0008 8390h rspi0 rspi command register 0 spcmd0 16 16 2, 3 pclkb 2 iclk 0008 8392h rspi0 rspi command register 1 spcmd1 16 16 2, 3 pclkb 2 iclk 0008 8394h rspi0 rspi command register 2 spcmd2 16 16 2, 3 pclkb 2 iclk 0008 8396h rspi0 rspi command register 3 spcmd3 16 16 2, 3 pclkb 2 iclk 0008 8398h rspi0 rspi command register 4 spcmd4 16 16 2, 3 pclkb 2 iclk 0008 839ah rspi0 rspi command register 5 spcmd5 16 16 2, 3 pclkb 2 iclk 0008 839ch rspi0 rspi command register 6 spcmd6 16 16 2, 3 pclkb 2 iclk 0008 839eh rspi0 rspi command register 7 spcmd7 16 16 2, 3 pclkb 2 iclk 0008 8600h mtu3 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8601h mtu4 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8602h mtu3 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8603h mtu4 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8604h mtu3 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk 0008 8605h mtu3 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk 0008 8606h mtu4 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk 0008 8607h mtu4 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk 0008 8608h mtu3 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8609h mtu4 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 860ah mtu timer output master enable register toer 8 8 2, 3 pclkb 2 iclk 0008 860dh mtu timer gate control register tgcr 8 8 2, 3 pclkb 2 iclk 0008 860eh mtu timer output control register 1 tocr1 8 8 2, 3 pclkb 2 iclk 0008 860fh mtu timer output control register 2 tocr2 8 8 2, 3 pclkb 2 iclk 0008 8610h mtu3 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8612h mtu4 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8614h mtu timer cycle data register tcdr 16 16 2, 3 pclkb 2 iclk 0008 8616h mtu timer dead time data register tddr 16 16 2, 3 pclkb 2 iclk 0008 8618h mtu3 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 861ah mtu3 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 861ch mtu4 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 861eh mtu4 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8620h mtu timer subcounter tcnts 16 16 2, 3 pclkb 2 iclk 0008 8622h mtu timer cycle buffer register tcbr 16 16 2, 3 pclkb 2 iclk 0008 8624h mtu3 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk 0008 8626h mtu3 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk 0008 8628h mtu4 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk 0008 862ah mtu4 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk 0008 862ch mtu3 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 862dh mtu4 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8630h mtu timer interrupt skipping set register titcr 8 8 2, 3 pclkb 2 iclk 0008 8631h mtu timer interrupt skipping counter titcnt 8 8 2, 3 pclkb 2 iclk 0008 8632h mtu timer buffer transfer set register tbter 8 8 2, 3 pclkb 2 iclk 0008 8634h mtu timer dead time enable register tder 8 8 2, 3 pclkb 2 iclk 0008 8636h mtu timer output level buffer register tolbr 8 8 2, 3 pclkb 2 iclk 0008 8638h mtu3 timer buffer operation transfer mode register tbtm 8 8 2, 3 pclkb 2 iclk 0008 8639h mtu4 timer buffer operation transfer mode register tbtm 8 8 2, 3 pclkb 2 iclk 0008 8640h mtu4 timer a/d converter start request control register tadcr 16 16 2, 3 pclkb 2 iclk 0008 8644h mtu4 timer a/d converter start request cycle set register a tadcora 16 16 2, 3 pclkb 2 iclk 0008 8646h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (14 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 72 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 8648h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16 2, 3 pclkb 2 iclk 0008 864ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 2, 3 pclkb 2 iclk 0008 8660h mtu timer waveform control register twcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8680h mtu timer start register tstr 8 8, 16 2, 3 pclkb 2 iclk 0008 8681h mtu timer synchronous register tsyr 8 8, 16 2, 3 pclkb 2 iclk 0008 8684h mtu timer read/write enable register trwer 8 8, 16 2, 3 pclkb 2 iclk 0008 8690h mtu0 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8691h mtu1 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8692h mtu2 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8693h mtu3 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8694h mtu4 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8695h mtu5 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8700h mtu0 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8701h mtu0 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8702h mtu0 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk 0008 8703h mtu0 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk 0008 8704h mtu0 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8705h mtu0 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8706h mtu0 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8708h mtu0 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 870ah mtu0 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 870ch mtu0 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk 0008 870eh mtu0 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk 0008 8720h mtu0 timer general register e tgre 16 16 2, 3 pclkb 2 iclk 0008 8722h mtu0 timer general register f tgrf 16 16 2, 3 pclkb 2 iclk 0008 8724h mtu0 timer interrupt enable register 2 tier2 8 8 2, 3 pclkb 2 iclk 0008 8726h mtu0 timer buffer operation transfer mode register tbtm 8 8 2, 3 pclkb 2 iclk 0008 8780h mtu1 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8781h mtu1 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8782h mtu1 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk 0008 8784h mtu1 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8785h mtu1 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8786h mtu1 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8788h mtu1 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 878ah mtu1 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8790h mtu1 timer input capture control register ticcr 8 8 2, 3 pclkb 2 iclk 0008 8800h mtu2 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8801h mtu2 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8802h mtu2 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk 0008 8804h mtu2 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8805h mtu2 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8806h mtu2 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8808h mtu2 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 880ah mtu2 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8880h mtu5 timer counter u tcntu 16 16 2, 3 pclkb 2 iclk 0008 8882h mtu5 timer general register u tgru 16 16 2, 3 pclkb 2 iclk 0008 8884h mtu5 timer control register u tcru 8 8 2, 3 pclkb 2 iclk 0008 8886h mtu5 timer i/o control register u tioru 8 8 2, 3 pclkb 2 iclk 0008 8890h mtu5 timer counter v tcntv 16 16 2, 3 pclkb 2 iclk 0008 8892h mtu5 timer general register v tgrv 16 16 2, 3 pclkb 2 iclk 0008 8894h mtu5 timer control register v tcrv 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (15 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 73 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 8896h mtu5 timer i/o control register v tiorv 8 8 2, 3 pclkb 2 iclk 0008 88a0h mtu5 timer counter w tcntw 16 16 2, 3 pclkb 2 iclk 0008 88a2h mtu5 timer general register w tgrw 16 16 2, 3 pclkb 2 iclk 0008 88a4h mtu5 timer control register w tcrw 8 8 2, 3 pclkb 2 iclk 0008 88a6h mtu5 timer i/o control register w tiorw 8 8 2, 3 pclkb 2 iclk 0008 88b2h mtu5 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 88b4h mtu5 timer start register tstr 8 8 2, 3 pclkb 2 iclk 0008 88b6h mtu5 timer compare match clear register tcntcmpclr 8 8 2, 3 pclkb 2 iclk 0008 8900h poe input level control/status register 1 icsr1 16 8, 16 2, 3 pclkb 2 iclk 0008 8902h poe output level control/status register 1 ocsr1 16 8, 16 2, 3 pclkb 2 iclk 0008 8908h poe input level control/status register 2 icsr2 16 8, 16 2, 3 pclkb 2 iclk 0008 890ah poe software port output enable register spoer 8 8 2, 3 pclkb 2 iclk 0008 890bh poe port output enable control register 1 poecr1 8 8 2, 3 pclkb 2 iclk 0008 890ch poe port output enable control register 2 poecr2 8 8 2, 3 pclkb 2 iclk 0008 890eh poe input level control/status register 3 icsr3 16 8, 16 2, 3 pclkb 2 iclk 0008 9000h s12ad a/d control register adcsr 16 16 2, 3 pclkb 2 iclk 0008 9004h s12ad a/d channel select register a adansa 16 16 2, 3 pclkb 2 iclk 0008 9008h s12ad a/d-converted value addition mode select register adads 16 16 2, 3 pclkb 2 iclk 0008 900ch s12ad a/d-converted value addition count select register adadc 8 8 2, 3 pclkb 2 iclk 0008 900eh s12ad a/d control extended register adcer 16 16 2, 3 pclkb 2 iclk 0008 9010h s12ad a/d start trigger select register adstrgr 16 16 2, 3 pclkb 2 iclk 0008 9012h s12ad a/d converted extended input control register adexicr 16 16 2, 3 pclkb 2 iclk 0008 9014h s12ad a/d channel select register b adansb 16 16 2, 3 pclkb 2 iclk 0008 9018h s12ad a/d double register addbldr 16 16 2, 3 pclkb 2 iclk 0008 901ah s12ad a/d temperature sensor data register adtsdr 16 16 2, 3 pclkb 2 iclk 0008 901ch s12ad a/d internal reference voltage data register adocdr 16 16 2, 3 pclkb 2 iclk 0008 901eh s12ad a/d self-diagnosis data register adrd 16 16 2, 3 pclkb 2 iclk 0008 9020h s12ad a/d data register 0 addr0 16 16 2, 3 pclkb 2 iclk 0008 9022h s12ad a/d data register 1 addr1 16 16 2, 3 pclkb 2 iclk 0008 9024h s12ad a/d data register 2 addr2 16 16 2, 3 pclkb 2 iclk 0008 9026h s12ad a/d data register 3 addr3 16 16 2, 3 pclkb 2 iclk 0008 9028h s12ad a/d data register 4 addr4 16 16 2, 3 pclkb 2 iclk 0008 902ah s12ad a/d data register 5 addr5 16 16 2, 3 pclkb 2 iclk 0008 902ch s12ad a/d data register 6 addr6 16 16 2, 3 pclkb 2 iclk 0008 902eh s12ad a/d data register 7 addr7 16 16 2, 3 pclkb 2 iclk 0008 9030h s12ad a/d data register 8 addr8 16 16 2, 3 pclkb 2 iclk 0008 9032h s12ad a/d data register 9 addr9 16 16 2, 3 pclkb 2 iclk 0008 9034h s12ad a/d data register 10 addr10 16 16 2, 3 pclkb 2 iclk 0008 9036h s12ad a/d data register 11 addr11 16 16 2, 3 pclkb 2 iclk 0008 9038h s12ad a/d data register 12 addr12 16 16 2, 3 pclkb 2 iclk 0008 903ah s12ad a/d data register 13 addr13 16 16 2, 3 pclkb 2 iclk 0008 903ch s12ad a/d data register 14 addr14 16 16 2, 3 pclkb 2 iclk 0008 903eh s12ad a/d data register 15 addr15 16 16 2, 3 pclkb 2 iclk 0008 9060h s12ad a/d sampling state register 0 adsstr0 8 8 2, 3 pclkb 2 iclk 0008 9061h s12ad a/d sampling state register l adsstrl 8 8 2, 3 pclkb 2 iclk 0008 9066h s12ad a/d sample and hold circuit register adshcr 16 16 2, 3 pclkb 2 iclk 0008 9070h s12ad a/d sampling state register t adsstrt 8 8 2, 3 pclkb 2 iclk 0008 9071h s12ad a/d sampling state register o adsstro 8 8 2, 3 pclkb 2 iclk 0008 9073h s12ad a/d sampling state register 1 adsstr1 8 8 2, 3 pclkb 2 iclk 0008 9074h s12ad a/d sampling state register 2 adsstr2 8 8 2, 3 pclkb 2 iclk 0008 9075h s12ad a/d sampling state register 3 adsstr3 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (16 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 74 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 9076h s12ad a/d sampling state register 4 adsstr4 8 8 2, 3 pclkb 2 iclk 0008 9077h s12ad a/d sampling state register 5 adsstr5 8 8 2, 3 pclkb 2 iclk 0008 9078h s12ad a/d sampling state register 6 adsstr6 8 8 2, 3 pclkb 2 iclk 0008 9079h s12ad a/d sampling state register 7 adsstr7 8 8 2, 3 pclkb 2 iclk 0008 907ah s12ad a/d disconnecting detection control register addiscr 8 8 2, 3 pclkb 2 iclk 0008 a000h sci0 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a001h sci0 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a002h sci0 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a003h sci0 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a004h sci0 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a005h sci0 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a006h sci0 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a007h sci0 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a008h sci0 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a009h sci0 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a00ah sci0 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a00bh sci0 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a00ch sci0 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a00dh sci0 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a020h sci1 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a021h sci1 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a022h sci1 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a023h sci1 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a024h sci1 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a025h sci1 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a026h sci1 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a027h sci1 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a028h sci1 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a029h sci1 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a02ah sci1 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a02bh sci1 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a02ch sci1 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a02dh sci1 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a040h sci2 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a041h sci2 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a042h sci2 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a043h sci2 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a044h sci2 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a045h sci2 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a046h sci2 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a047h sci2 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a048h sci2 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a049h sci2 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a04ah sci2 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a04bh sci2 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a04ch sci2 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a04dh sci2 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a060h sci3 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a061h sci3 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a062h sci3 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a063h sci3 transmit data register tdr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (17 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 75 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 a064h sci3 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a065h sci3 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a066h sci3 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a067h sci3 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a068h sci3 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a069h sci3 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a06ah sci3 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a06bh sci3 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a06ch sci3 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a06dh sci3 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a080h sci4 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a081h sci4 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a082h sci4 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a083h sci4 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a084h sci4 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a085h sci4 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a086h sci4 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a087h sci4 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a088h sci4 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a089h sci4 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a08ah sci4 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a08bh sci4 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a08ch sci4 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a08dh sci4 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a0a0h sci5 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a0a1h sci5 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a0a2h sci5 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a0a3h sci5 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a0a4h sci5 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a0a5h sci5 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a0a6h sci5 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a0a7h sci5 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a0a8h sci5 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a0a9h sci5 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a0aah sci5 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a0abh sci5 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a0ach sci5 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a0adh sci5 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a0c0h sci6 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a0c1h sci6 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a0c2h sci6 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a0c3h sci6 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a0c4h sci6 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a0c5h sci6 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a0c6h sci6 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a0c7h sci6 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a0c8h sci6 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a0c9h sci6 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a0cah sci6 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a0cbh sci6 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a0cch sci6 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (18 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 76 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 a0cdh sci6 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a0e0h sci7 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a0e1h sci7 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a0e2h sci7 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a0e3h sci7 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a0e4h sci7 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a0e5h sci7 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a0e6h sci7 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a0e7h sci7 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a0e8h sci7 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a0e9h sci7 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a0eah sci7 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a0ebh sci7 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a0ech sci7 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a0edh sci7 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a100h sci8 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a101h sci8 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a102h sci8 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a103h sci8 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a104h sci8 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a105h sci8 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a106h sci8 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a107h sci8 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a108h sci8 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a109h sci8 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a10ah sci8 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a10bh sci8 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a10ch sci8 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a10dh sci8 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a120h sci9 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a121h sci9 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a122h sci9 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a123h sci9 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a124h sci9 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a125h sci9 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a126h sci9 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a127h sci9 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a128h sci9 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a129h sci9 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a12ah sci9 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a12bh sci9 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a12ch sci9 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a12dh sci9 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a140h sci10 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a141h sci10 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a142h sci10 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a143h sci10 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a144h sci10 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a145h sci10 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a146h sci10 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a147h sci10 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (19 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 77 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 a148h sci10 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a149h sci10 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a14ah sci10 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a14bh sci10 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a14ch sci10 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a14dh sci10 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a160h sci11 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a161h sci11 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a162h sci11 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a163h sci11 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a164h sci11 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a165h sci11 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a166h sci11 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a167h sci11 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a168h sci11 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a169h sci11 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a16ah sci11 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a16bh sci11 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a16ch sci11 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a16dh sci11 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 b000h cac cac control register 0 cacr0 8 8 2, 3 pclkb 2 iclk 0008 b001h cac cac control register 1 cacr1 8 8 2, 3 pclkb 2 iclk 0008 b002h cac cac control register 2 cacr2 8 8 2, 3 pclkb 2 iclk 0008 b003h cac cac interrupt control register caicr 8 8 2, 3 pclkb 2 iclk 0008 b004h cac cac status register castr 8 8 2, 3 pclkb 2 iclk 0008 b006h cac cac upper-limit value setting register caulvr 16 16 2, 3 pclkb 2 iclk 0008 b008h cac cac lower-limit value setting register callvr 16 16 2, 3 pclkb 2 iclk 0008 b00ah cac cac counter buffer register cacntbr 16 16 2, 3 pclkb 2 iclk 0008 b080h doc doc control register docr 8 8 2, 3 pclkb 2 iclk 0008 b082h doc doc data input register dodir 16 16 2, 3 pclkb 2 iclk 0008 b084h doc doc data setting register dodsr 16 16 2, 3 pclkb 2 iclk 0008 b100h elc event link control register elcr 8 8 2, 3 pclkb 2 iclk 0008 b102h elc event link setting register 1 elsr1 8 8 2, 3 pclkb 2 iclk 0008 b103h elc event link setting register 2 elsr2 8 8 2, 3 pclkb 2 iclk 0008 b104h elc event link setting register 3 elsr3 8 8 2, 3 pclkb 2 iclk 0008 b105h elc event link setting register 4 elsr4 8 8 2, 3 pclkb 2 iclk 0008 b108h elc event link setting register 7 elsr7 8 8 2, 3 pclkb 2 iclk 0008 b10bh elc event link setting register 10 elsr10 8 8 2, 3 pclkb 2 iclk 0008 b10dh elc event link setting register 12 elsr12 8 8 2, 3 pclkb 2 iclk 0008 b110h elc event link setting register 15 elsr15 8 8 2, 3 pclkb 2 iclk 0008 b111h elc event link setting register 16 elsr16 8 8 2, 3 pclkb 2 iclk 0008 b113h elc event link setting register 18 elsr18 8 8 2, 3 pclkb 2 iclk 0008 b114h elc event link setting register 19 elsr19 8 8 2, 3 pclkb 2 iclk 0008 b115h elc event link setting register 20 elsr20 8 8 2, 3 pclkb 2 iclk 0008 b116h elc event link setting register 21 elsr21 8 8 2, 3 pclkb 2 iclk 0008 b117h elc event link setting register 22 elsr22 8 8 2, 3 pclkb 2 iclk 0008 b118h elc event link setting register 23 elsr23 8 8 2, 3 pclkb 2 iclk 0008 b119h elc event link setting register 24 elsr24 8 8 2, 3 pclkb 2 iclk 0008 b11ah elc event link setting register 25 elsr25 8 8 2, 3 pclkb 2 iclk 0008 b11bh elc event link setting register 26 elsr26 8 8 2, 3 pclkb 2 iclk 0008 b11ch elc event link setting register 27 elsr27 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (20 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 78 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 b11dh elc event link setting register 28 elsr28 8 8 2, 3 pclkb 2 iclk 0008 b11eh elc event link setting register 29 elsr29 8 8 2, 3 pclkb 2 iclk 0008 b11fh elc event link option setting register a elopa 8 8 2, 3 pclkb 2 iclk 0008 b120h elc event link option setting register b elopb 8 8 2, 3 pclkb 2 iclk 0008 b121h elc event link option setting register c elopc 8 8 2, 3 pclkb 2 iclk 0008 b122h elc event link option setting register d elopd 8 8 2, 3 pclkb 2 iclk 0008 b123h elc port group setting register 1 pgr1 8 8 2, 3 pclkb 2 iclk 0008 b124h elc port group setting register 2 pgr2 8 8 2, 3 pclkb 2 iclk 0008 b125h elc port group control register 1 pgc1 8 8 2, 3 pclkb 2 iclk 0008 b126h elc port group control register 2 pgc2 8 8 2, 3 pclkb 2 iclk 0008 b127h elc port buffer register 1 pdbf1 8 8 2, 3 pclkb 2 iclk 0008 b128h elc port buffer register 2 pdbf2 8 8 2, 3 pclkb 2 iclk 0008 b129h elc event link port setting register 0 pel0 8 8 2, 3 pclkb 2 iclk 0008 b12ah elc event link port setting register 1 pel1 8 8 2, 3 pclkb 2 iclk 0008 b12bh elc event link port setting register 2 pel2 8 8 2, 3 pclkb 2 iclk 0008 b12ch elc event link port setting register 3 pel3 8 8 2, 3 pclkb 2 iclk 0008 b12dh elc event link software event generation register elsegr 8 8 2, 3 pclkb 2 iclk 0008 b300h sci12 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 b301h sci12 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 b302h sci12 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 b303h sci12 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 b304h sci12 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 b305h sci12 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 b306h sci12 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 b307h sci12 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 b308h sci12 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 b309h sci12 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 b30ah sci12 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 b30bh sci12 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 b30ch sci12 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 b30dh sci12 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 b320h sci12 extended serial mode enable register esmer 8 8 2, 3 pclkb 2 iclk 0008 b321h sci12 control register 0 cr0 8 8 2, 3 pclkb 2 iclk 0008 b322h sci12 control register 1 cr1 8 8 2, 3 pclkb 2 iclk 0008 b323h sci12 control register 2 cr2 8 8 2, 3 pclkb 2 iclk 0008 b324h sci12 control register 3 cr3 8 8 2, 3 pclkb 2 iclk 0008 b325h sci12 port control register pcr 8 8 2, 3 pclkb 2 iclk 0008 b326h sci12 interrupt control register icr 8 8 2, 3 pclkb 2 iclk 0008 b327h sci12 status register str 8 8 2, 3 pclkb 2 iclk 0008 b328h sci12 status clear register stcr 8 8 2, 3 pclkb 2 iclk 0008 b329h sci12 control field 0 data register cf0dr 8 8 2, 3 pclkb 2 iclk 0008 b32ah sci12 control field 0 compare enable register cf0cr 8 8 2, 3 pclkb 2 iclk 0008 b32bh sci12 control field 0 receive data register cf0rr 8 8 2, 3 pclkb 2 iclk 0008 b32ch sci12 primary control field 1 data register pcf1dr 8 8 2, 3 pclkb 2 iclk 0008 b32dh sci12 secondary control field 1 data register scf1dr 8 8 2, 3 pclkb 2 iclk 0008 b32eh sci12 control field 1 compare enable register cf1cr 8 8 2, 3 pclkb 2 iclk 0008 b32fh sci12 control field 1 receive data register cf1rr 8 8 2, 3 pclkb 2 iclk 0008 b330h sci12 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 b331h sci12 timer mode register tmr 8 8 2, 3 pclkb 2 iclk 0008 b332h sci12 timer prescaler register tpre 8 8 2, 3 pclkb 2 iclk 0008 b333h sci12 timer count register tcnt 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (21 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 79 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 c000h port0 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c001h port1 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c002h port2 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c003h port3 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c004h port4 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c005h port5 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c006h port6 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c007h port7 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c008h port8 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c009h port9 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00ah porta port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00bh portb port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00ch portc port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00dh portd port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00eh porte port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00fh portf port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c011h porth port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c012h portj port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c013h portk port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c014h portl port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c020h port0 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c021h port1 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c022h port2 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c023h port3 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c024h port4 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c025h port5 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c026h port6 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c027h port7 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c028h port8 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c029h port9 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02ah porta port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02bh portb port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02ch portc port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02eh porte port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02fh portf port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c031h porth port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c032h portj port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c033h portk port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c034h portl port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c040h port0 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c041h port1 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing table 4.1 list of i/o register s (address order) (22 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 80 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 c042h port2 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c043h port3 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c044h port4 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c045h port5 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c046h port6 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c047h port7 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c048h port8 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c049h port9 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pc l kb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04ah porta port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04bh portb port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing table 4.1 list of i/o register s (address order) (23 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 81 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 c04ch portc port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04dh portd port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04eh porte port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04fh portf port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c051h porth port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c052h portj port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c053h portk port input data register pidr 8 8 2, 3 pclkb 2 iclk 0008 c054h portl port input data register pidr 8 8 2, 3 pclkb 2 iclk 0008 c060h port0 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c061h port1 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c062h port2 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c063h port3 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c064h port4 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c065h port5 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c066h port6 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c067h port7 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c068h port8 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c069h port9 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06ah porta port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06bh portb port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06ch portc port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06dh portd port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06eh porte port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06fh portf port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c071h porth port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c072h portj port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c073h portk port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c074h portl port mode register pmr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (24 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 82 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 c080 port0 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c082h port1 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c083h port1 open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c084h port2 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c085h port2 open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c086h port3 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c087h port3 open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c08ch port6 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c08eh port7 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c08fh port7 open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c090h port8 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c092h port9 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c094h porta open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c095h porta open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c096h portb open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c097h portb open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c098h portc open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c099h portc open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c09ch porte open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c09dh porte open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c0a6h portk open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c0a7h portk open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c0c0h port0 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c1h port1 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c2h port2 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c3h port3 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c4h port4 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c5h port5 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c6h port6 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c7h port7 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c8h port8 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c9h port9 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0cah porta pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0cbh portb pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0cch portc pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0cdh portd pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0ceh porte pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0cfh portf pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0d1h porth pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0d2h portj pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0d3h portk pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0d4h portl pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0e0h port0 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0e1h port1 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0e2h port2 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0e3h port3 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0e5h port5 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0e6h port6 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0e7h port7 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0e8h port8 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0e9h port9 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (25 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 83 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 c0eah porta drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0ebh portb drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0ech portc drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0edh portd drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0eeh porte drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0f1h porth drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0f2h portj drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0f3h portk drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c100h mpc cs output enable register pfcse 8 8 2, 3 pclkb 2 iclk 0008 c104h mpc address output enable register 0 pfaoe0 8 8, 16 2, 3 pclkb 2 iclk 0008 c105h mpc address output enable register 1 pfaoe1 8 8, 16 2, 3 pclkb 2 iclk 0008 c106h mpc external bus control register 0 pfbcr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c107h mpc external bus control register 1 pfbcr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c11fh mpc write-protect register pwpr 8 8 2, 3 pclkb 2 iclk 0008 c140h mpc p00 pin function control register p00pfs 8 8 2, 3 pclkb 2 iclk 0008 c141h mpc p01 pin function control register p01pfs 8 8 2, 3 pclkb 2 iclk 0008 c142h mpc p02 pin function control register p02pfs 8 8 2, 3 pclkb 2 iclk 0008 c143h mpc p03 pin function control register p03pfs 8 8 2, 3 pclkb 2 iclk 0008 c145h mpc p05 pin function control register p05pfs 8 8 2, 3 pclkb 2 iclk 0008 c147h mpc p07 pin function control register p07pfs 8 8 2, 3 pclkb 2 iclk 0008 c14ah mpc p12 pin function control register p12pfs 8 8 2, 3 pclkb 2 iclk 0008 c14bh mpc p13 pin function control register p13pfs 8 8 2, 3 pclkb 2 iclk 0008 c14ch mpc p14 pin function control register p14pfs 8 8 2, 3 pclkb 2 iclk 0008 c14dh mpc p15 pin function control register p15pfs 8 8 2, 3 pclkb 2 iclk 0008 c14eh mpc p16 pin function control register p16pfs 8 8 2, 3 pclkb 2 iclk 0008 c14fh mpc p17 pin function control register p17pfs 8 8 2, 3 pclkb 2 iclk 0008 c150h mpc p20 pin function control register p20pfs 8 8 2, 3 pclkb 2 iclk 0008 c151h mpc p21 pin function control register p21pfs 8 8 2, 3 pclkb 2 iclk 0008 c152h mpc p22 pin function control register p22pfs 8 8 2, 3 pclkb 2 iclk 0008 c153h mpc p23 pin function control register p23pfs 8 8 2, 3 pclkb 2 iclk 0008 c154h mpc p24 pin function control register p24pfs 8 8 2, 3 pclkb 2 iclk 0008 c155h mpc p25 pin function control register p25pfs 8 8 2, 3 pclkb 2 iclk 0008 c156h mpc p26 pin function control register p26pfs 8 8 2, 3 pclkb 2 iclk 0008 c157h mpc p27 pin function control register p27pfs 8 8 2, 3 pclkb 2 iclk 0008 c158h mpc p30 pin function control register p30pfs 8 8 2, 3 pclkb 2 iclk 0008 c159h mpc p31 pin function control register p31pfs 8 8 2, 3 pclkb 2 iclk 0008 c15ah mpc p32 pin function control register p32pfs 8 8 2, 3 pclkb 2 iclk 0008 c15bh mpc p33 pin function control register p33pfs 8 8 2, 3 pclkb 2 iclk 0008 c15ch mpc p34 pin function control register p34pfs 8 8 2, 3 pclkb 2 iclk 0008 c160h mpc p40 pin function control register p40pfs 8 8 2, 3 pclkb 2 iclk 0008 c161h mpc p41 pin function control register p41pfs 8 8 2, 3 pclkb 2 iclk 0008 c162h mpc p42 pin function control register p42pfs 8 8 2, 3 pclkb 2 iclk 0008 c163h mpc p43 pin function control register p43pfs 8 8 2, 3 pclkb 2 iclk 0008 c164h mpc p44 pin function control register p44pfs 8 8 2, 3 pclkb 2 iclk 0008 c165h mpc p45 pin function control register p45pfs 8 8 2, 3 pclkb 2 iclk 0008 c166h mpc p46 pin function control register p46pfs 8 8 2, 3 pclkb 2 iclk 0008 c167h mpc p47 pin function control register p47pfs 8 8 2, 3 pclkb 2 iclk 0008 c168h mpc p50 pin function control register p50pfs 8 8 2, 3 pclkb 2 iclk 0008 c169h mpc p51 pin function control register p51pfs 8 8 2, 3 pclkb 2 iclk 0008 c16ah mpc p52 pin function control register p52pfs 8 8 2, 3 pclkb 2 iclk 0008 c16ch mpc p54 pin function control register p54pfs 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (26 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 84 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 c16dh mpc p55 pin function control register p55pfs 8 8 2, 3 pclkb 2 iclk 0008 c16eh mpc p56 pin function control register p56pfs 8 8 2, 3 pclkb 2 iclk 0008 c170h mpc p60 pin function control register p60pfs 8 8 2, 3 pclkb 2 iclk 0008 c171h mpc p61 pin function control register p61pfs 8 8 2, 3 pclkb 2 iclk 0008 c178h mpc p70 pin function control register p70pfs 8 8 2, 3 pclkb 2 iclk 0008 c17ch mpc p74 pin function control register p74pfs 8 8 2, 3 pclkb 2 iclk 0008 c17dh mpc p75 pin function control register p75pfs 8 8 2, 3 pclkb 2 iclk 0008 c17eh mpc p76 pin function control register p76pfs 8 8 2, 3 pclkb 2 iclk 0008 c17fh mpc p77 pin function control register p77pfs 8 8 2, 3 pclkb 2 iclk 0008 c180h mpc p80 pin function control register p80pfs 8 8 2, 3 pclkb 2 iclk 0008 c181h mpc p81 pin function control register p81pfs 8 8 2, 3 pclkb 2 iclk 0008 c182h mpc p82 pin function control register p82pfs 8 8 2, 3 pclkb 2 iclk 0008 c183h mpc p83 pin function control register p83pfs 8 8 2, 3 pclkb 2 iclk 0008 c186h mpc p86 pin function control register p865pfs 8 8 2, 3 pclkb 2 iclk 0008 c187h mpc p87 pin function control register p87pfs 8 8 2, 3 pclkb 2 iclk 0008 c188h mpc p90 pin function control register p90pfs 8 8 2, 3 pclkb 2 iclk 0008 c189h mpc p91 pin function control register p91pfs 8 8 2, 3 pclkb 2 iclk 0008 c18ah mpc p92 pin function control register p92pfs 8 8 2, 3 pclkb 2 iclk 0008 c18bh mpc p93 pin function control register p93pfs 8 8 2, 3 pclkb 2 iclk 0008 c190h mpc pa0 pin function control register pa0pfs 8 8 2, 3 pclkb 2 iclk 0008 c191h mpc pa1 pin function control register pa1pfs 8 8 2, 3 pclkb 2 iclk 0008 c192h mpc pa2 pin function control register pa2pfs 8 8 2, 3 pclkb 2 iclk 0008 c193h mpc pa3 pin function control register pa3pfs 8 8 2, 3 pclkb 2 iclk 0008 c194h mpc pa4 pin function control register pa4pfs 8 8 2, 3 pclkb 2 iclk 0008 c195h mpc pa5 pin function control register pa5pfs 8 8 2, 3 pclkb 2 iclk 0008 c196h mpc pa6 pin function control register pa6pfs 8 8 2, 3 pclkb 2 iclk 0008 c197h mpc pa7 pin function control register pa7pfs 8 8 2, 3 pclkb 2 iclk 0008 c198h mpc pb0 pin function control register pb0pfs 8 8 2, 3 pclkb 2 iclk 0008 c199h mpc pb1 pin function control register pb1pfs 8 8 2, 3 pclkb 2 iclk 0008 c19ah mpc pb2 pin function control register pb2pfs 8 8 2, 3 pclkb 2 iclk 0008 c19bh mpc pb3 pin function control register pb3pfs 8 8 2, 3 pclkb 2 iclk 0008 c19ch mpc pb4 pin function control register pb4pfs 8 8 2, 3 pclkb 2 iclk 0008 c19dh mpc pb5 pin function control register pb5pfs 8 8 2, 3 pclkb 2 iclk 0008 c19eh mpc pb6 pin function control register pb6pfs 8 8 2, 3 pclkb 2 iclk 0008 c19fh mpc pb7 pin function control register pb7pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a0h mpc pc0 pin function control register pc0pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a1h mpc pc1 pin function control register pc1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a2h mpc pc2 pin function control register pc2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a3h mpc pc3 pin function control register pc3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a4h mpc pc4 pin function control register pc4pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a5h mpc pc5 pin function control register pc5pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a6h mpc pc6 pin function control register pc6pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a7h mpc pc7 pin function control register pc7pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a8h mpc pd0 pin function control register pd0pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a9h mpc pd1 pin function control register pd1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1aah mpc pd2 pin function control register pd2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1abh mpc pd3 pin function control register pd3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1ach mpc pd4 pin function control register pd4pfs 8 8 2, 3 pclkb 2 iclk 0008 c1adh mpc pd5 pin function control register pd5pfs 8 8 2, 3 pclkb 2 iclk 0008 c1aeh mpc pd6 pin function control register pd6pfs 8 8 2, 3 pclkb 2 iclk 0008 c1afh mpc pd7 pin function control register pd7pfs 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (27 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 85 of 221 oct 18, 2013 rx210 group 4. i/o registers 0008 c1b0h mpc pe0 pin function control register pe0pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b1h mpc pe1 pin function control register pe1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b2h mpc pe2 pin function control register pe2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b3h mpc pe3 pin function control register pe3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b4h mpc pe4 pin function control register pe4pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b5h mpc pe5 pin function control register pe5pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b6h mpc pe6 pin function control register pe6pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b7h mpc pe7 pin function control register pe7pfs 8 8 2, 3 pclkb 2 iclk 0008 c1bdh mpc pf5 pin function control register pf5pfs 8 8 2, 3 pclkb 2 iclk 0008 c1c8h mpc ph0 pin function control register ph0pfs 8 8 2, 3 pclkb 2 iclk 0008 c1c9h mpc ph1 pin function control register ph1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1cah mpc ph2 pin function control register ph2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1cbh mpc ph3 pin function control register ph3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1d1h mpc pj1 pin function control register pj1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1d3h mpc pj3 pin function control register pj3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1dah mpc pk2 pin function control register pk2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1dbh mpc pk3 pin function control register pk3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1dch mpc pk4 pin function control register pk4pfs 8 8 2, 3 pclkb 2 iclk 0008 c1ddh mpc pk5 pin function control register pk5pfs 8 8 2, 3 pclkb 2 iclk 0008 c280h system deep standby control register dpsbycr 8 8 4, 5 pclkb 2, 3 iclk 0008 c282h system deep standby interrupt enable register 0 dpsier0 8 8 4, 5 pclkb 2, 3 iclk 0008 c284h system deep standby interrupt enable register 2 dpsier2 8 8 4, 5 pclkb 2, 3 iclk 0008 c286h system deep standby interrupt flag register 0 dpsifr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c288h system deep standby interrupt flag register 2 dpsifr2 8 8 4, 5 pclkb 2, 3 iclk 0008 c28ah system deep standby interrupt edge register 0 dpsiegr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c28ch system deep standby interrupt edge register 2 dpsiegr2 8 8 4, 5 pclkb 2, 3 iclk 0008 c28fh system flash hoco software standby control register fhssbycr 8 8 4, 5 pclkb 2, 3 iclk 0008 c290h system reset status register 0 rstsr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c291h system reset status register 1 rstsr1 8 8 4, 5 pclkb 2, 3 iclk 0008 c293h system main clock oscillator forced oscillation control register mofcr 8 8 4, 5 pclkb 2, 3 iclk 0008 c294h system high-speed clock oscillator power su pply control register hocopcr 8 8 4, 5 pclkb 2, 3 iclk 0008 c295h system pll power control register pllpcr 8 8 4, 5 pclkb 2, 3 iclk 0008 c296h flash flash write erase protection register fwepror 8 8 4, 5 pclkb 2, 3 iclk 0008 c297h system voltage monitoring circuit/comparator a control register lvcmpcr 8 8 4, 5 pclkb 2, 3 iclk 0008 c298h system voltage detection level select register lvdlvlr 8 8 4, 5 pclkb 2, 3 iclk 0008 c29ah system voltage monitoring 1 circuit/comparator a1 control register 0 lvd1cr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c29bh system voltage monitoring 2 circuit/comparator a2 control register 0 lvd2cr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c2a0h to 0008 c2bfh system deep standby backup register 0 to 31 dpsbkr0 to dpsbkr31 8 8 4, 5 pclkb 2, 3 iclk 0008 c400h rtc 64-hz counter r64cnt 8 8 2, 3 pclkb 2 iclk 0008 c402h rtc second counter rseccnt 8 8 2, 3 pclkb 2 iclk 0008 c404h rtc minute counter rmincnt 8 8 2, 3 pclkb 2 iclk 0008 c406h rtc hour counter rhrcnt 8 8 2, 3 pclkb 2 iclk 0008 c408h rtc day-of-week counter rwkcnt 8 8 2, 3 pclkb 2 iclk 0008 c40ah rtc date counter rdaycnt 8 8 2, 3 pclkb 2 iclk 0008 c40ch rtc month counter rmoncnt 8 8 2, 3 pclkb 2 iclk 0008 c40eh rtc year counter ryrcnt 16 16 2, 3 pclkb 2 iclk 0008 c410h rtc second alarm register rsecar 8 8 2, 3 pclkb 2 iclk 0008 c412h rtc minute alarm register rminar 8 8 2, 3 pclkb 2 iclk 0008 c414h rtc hour alarm register rhrar 8 8 2, 3 pclkb 2 iclk 0008 c416h rtc day-of-week alarm register rwkar 8 8 2, 3 pclkb 2 iclk 0008 c418h rtc date alarm register rdayar 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (28 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 86 of 221 oct 18, 2013 rx210 group 4. i/o registers note 1. odd addresses cannot be accessed in 16-bit units. when accessing a register in 16-bit units, access the address of the t mr0 or tmr2 register. note 2. odd addresses cannot be accessed in 16-bit units. when accessing a register in 16-bit units, access the address of the t mocntl register. 0008 c41ah rtc month alarm register rmonar 8 8 2, 3 pclkb 2 iclk 0008 c41ch rtc year alarm register ryrar 16 16 2, 3 pclkb 2 iclk 0008 c41eh rtc year alarm enable register ryraren 8 8 2, 3 pclkb 2 iclk 0008 c422h rtc rtc control register 1 rcr1 8 8 2, 3 pclkb 2 iclk 0008 c424h rtc rtc control register 2 rcr2 8 8 2, 3 pclkb 2 iclk 0008 c426h rtc rtc control register 3 rcr3 8 8 2, 3 pclkb 2 iclk 0008 c42eh rtc time error adjustment register radj 8 8 2, 3 pclkb 2 iclk 0008 c440h rtc time capture control register 0 rtccr0 8 8 2, 3 pclkb 2 iclk 0008 c442h rtc time capture control register 1 rtccr1 8 8 2, 3 pclkb 2 iclk 0008 c444h rtc time capture control register 2 rtccr2 8 8 2, 3 pclkb 2 iclk 0008 c452h rtc second capture register 0 rseccp0 8 8 2, 3 pclkb 2 iclk 0008 c454h rtc minute capture register 0 rmincp0 8 8 2, 3 pclkb 2 iclk 0008 c456h rtc hour capture register 0 rhrcp0 8 8 2, 3 pclkb 2 iclk 0008 c45ah rtc date capture register 0/ rdaycp0 8 8 2, 3 pclkb 2 iclk 0008 c45ch rtc month capture register 0 rmoncp0 8 8 2, 3 pclkb 2 iclk 0008 c462h rtc second capture register 1 rseccp1 8 8 2, 3 pclkb 2 iclk 0008 c464h rtc minute capture register 1 rmincp1 8 8 2, 3 pclkb 2 iclk 0008 c466h rtc hour capture register 1 rhrcp1 8 8 2, 3 pclkb 2 iclk 0008 c46ah rtc date capture register 1 rdaycp1 8 8 2, 3 pclkb 2 iclk 0008 c46ch rtc month capture register 1 rmoncp1 8 8 2, 3 pclkb 2 iclk 0008 c472h rtc second capture register 2 rseccp2 8 8 2, 3 pclkb 2 iclk 0008 c474h rtc minute capture register 2 rmincp2 8 8 2, 3 pclkb 2 iclk 0008 c476h rtc hour capture register 2 rhrcp2 8 8 2, 3 pclkb 2 iclk 0008 c47ah rtc date capture register 2 rdaycp2 8 8 2, 3 pclkb 2 iclk 0008 c47ch rtc month capture register 2 rmoncp2 8 8 2, 3 pclkb 2 iclk 0008 c500h temps temperature sensor control register tscr 8 8 2, 3 pclkb 2 iclk 0008 c580h cmpb comparator b control register 1 cpbcnt1 8 8 2, 3 pclkb 2 iclk 0008 c582h cmpb comparator b flag register cpbflg 8 8 2, 3 pclkb 2 iclk 0008 c583h cmpb comparator b interrupt control register cpbint 8 8 2, 3 pclkb 2 iclk 0008 c584h cmpb comparator b filter select register cpbf 8 8 2, 3 pclkb 2 iclk 007f c402h flash flash mode register fmodr 8 8 2, 3 fclk 2 iclk 007f c410h flash flash access status register fastat 8 8 2, 3 fclk 2 iclk 007f c411h flash flash access error interrupt enable register faeint 8 8 2, 3 fclk 2 iclk 007f c412h flash flash ready interrupt enable register frdyie 8 8 2, 3 fclk 2 iclk 007f c440h flash e2 dataflash read enable register 0 dflre0 16 16 2, 3 fclk 2 iclk 007f c450h flash e2 dataflash programming/erasure enable register 0 dflwe0 16 16 2, 3 fclk 2 iclk 007f c454h flash fcu ram enable register fcurame 16 16 2, 3 fclk 2 iclk 007f ffb0h flash flash status register 0 fstatr0 8 8 2, 3 fclk 2 iclk 007f ffb1h flash flash status register 1 fstatr1 8 8 2, 3 fclk 2 iclk 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2, 3 fclk 2 iclk 007f ffb4h flash flash protection register fprotr 16 16 2, 3 fclk 2 iclk 007f ffb6h flash flash reset register fresetr 16 16 2, 3 fclk 2 iclk 007f ffbah flash fcu command register fcmdr 16 16 2, 3 fclk 2 iclk 007f ffc8h flash fcu processing switching register fcpsr 16 16 2, 3 fclk 2 iclk 007f ffcah flash e2 dataflash blank check control register dflbccnt 16 16 2, 3 fclk 2 iclk 007f ffcch flash flash p/e status register fpestat 16 16 2, 3 fclk 2 iclk 007f ffceh flash e2 dataflash blank check status register dflbcstat 16 16 2, 3 fclk 2 iclk 007f ffe8h flash peripheral clock notification register pckar 16 16 2, 3 fclk 2 iclk table 4.1 list of i/o register s (address order) (29 / 29) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk
r01ds0041ej0150 rev.1.50 page 87 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the lsi may result if absolute maximum ratings are exceeded. to preclude any malfunctions due to noise interferences, insert capacitors of high frequency characteristics between the vcc and vss pins, between the avcc0 and avss0 pins, and between the vrefh0 and vrefl0 pins. place capacitors of 0.1 f or so as close to every power pin and use the shortest and heaviest possible traces. connect the vcl pin to a vss pin via a 0.1 f (20% accuracy) capacitor. the capacitor must be placed as close to the pin as possible. note 1. ports 12, 13, 16, and 17 are 5 v tolerant. note 2. connect avcc0 to vcc. when neither the a/d converter nor the d/a converter is in use, do not leave the avcc0, vrefh, vrefh0, avss0, vrefl, and vrefl0 pins open. connect the av cc0, vrefh, and vrefh0 pins to vcc, and the avss0, vrefl, and vrefl0 pins to vss, respectively. note 3. the maximum value is 6.5 v. table 5.1 absolute maximum ratings conditions: vss = avss0 = vrefl = vrefl0 = 0 v item symbol value unit power supply voltage vcc ?0.3 to +6.5 v input voltage (except for ports for 5 v tolerant* 1 )v in ?0.3 to vcc +0.3* 3 v input voltage (ports for 5 v tolerant* 1 )v in ?0.3 to +6.5 v reference power supply voltage vrefh, vrefh0 ?0.3 to vcc +0.3* 3 v analog power supply voltage avcc0* 2 ?0.3 to +6.5 v analog input voltage v an ?0.3 to vcc +0.3* 3 v operating temperature t opr ?40 to +105 c storage temperature t stg ?55 to +125 c
r01ds0041ej0150 rev.1.50 page 88 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.2 dc characteristics table 5.2 dc characteristics (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions schmitt trigger input voltage riic input pin (except for smbus, 5 v tolerant) v ih vcc 0.7 ? 5.8 v ports 12, 13, 16, and 17 (5 v tolerant) vcc 0.8 ? 5.8 ports 0, 14, 15, 2 to 9, a to l, and res# vcc 0.8 ? vcc + 0.3 riic input pin (except for smbus) v il ?0.3 ? vcc 0.3 other than riic input pin ?0.3 ? vcc 0.2 riic input pin (except for smbus) ?v t vcc 0.05 ? ? other than riic input pin vcc 0.1 ? ? input level voltage (except for schmitt trigger input pins) md pin v ih vcc 0.9 ? vcc + 0.3 v extal, wait# vcc 0.8 ? vcc + 0.3 d0 to d15 vcc 0.7 ? vcc + 0.3 riic input pin (smbus) 2.1 ? vcc + 0.3 md pin v il ?0.3 ? vcc 0.1 extal, wait# ?0.3 ? vcc 0.2 d0 to d15 ?0.3 ? vcc 0.3 riic input pin (smbus) ?0.3 ? 0.8 table 5.3 dc characteristics (2) conditions: vcc = avcc0 = 1.62 to 2.7 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions schmitt trigger input voltage ports 12, 13, 16, and 17 (5 v tolerant) v ih vcc 0.8 ? 5.8 v ports 0, 14, 15, 2 to 9, a to l, and res# vcc 0.8 ? vcc + 0.3 all input pins v il ?0.3 ? vcc 0.2 ports 0 to 9, a to l vcc 2.2v ?v t vcc 0.05 ? ? vcc < 2.2v vcc 0.01 res# vcc 0.1 input level voltage (except for schmitt trigger input pins) md pin v ih vcc 0.9 ? vcc + 0.3 v extal, wait# vcc 0.8 ? vcc + 0.3 d0 to d15 vcc 0.7 ? vcc + 0.3 md pin v il ?0.3 ? vcc 0.1 extal, wait# ?0.3 ? vcc 0.2 d0 to d15 ?0.3 ? vcc 0.3
r01ds0041ej0150 rev.1.50 page 89 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version a] note 1. supply current values do not include output charge/disc harge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peri pheral functions is stopped. this does not include bgo operation. the clock source is pll and th e vco oscillation frequency is 100 mhz. bclk, fclk, and pclk are set to divided by 64. note 3. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is pll and the vc o oscillation frequency is 100 mhz. bclk, fclk, and pclk are iclk divided by 2. note 4. this is the increase if data is programmed to or er asing from the rom or e2 dataflash during program execution. table 5.4 dc characteristics (3) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions input leakage current res#, md pin, p35/nmi ? i in ? ??1.0av in = 0 v, vcc three-state leakage current (off-state) port 4 ? i tsi ? ??1.0av in = 0 v, vcc other pins except for ports for 5 v tolerant and port 4 ??0.2 ports for 5 v tolerant ? ? 1.0 v in = 0 v, 5.8 v input capacitance all input pins (except for ports 12, 13, 16, 17, 4, a1, a3, a4, and e) c in ? ? 15 pf v in = 0 v, f = 1 mhz, t a = 25c ports 12, 13, 16, 17, 4, a1, a3, a4, and e ? ? 30 table 5.5 dc characteristics (4) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit test conditions 1.62 to 2.7 v 2.7 to 4.0 v 4.0 to 5.5 v min. max. min. max. min. max. input pull-up mos current all ports (except for port 35) i p ?150 ?5 ?200 ?10 ?400 ?50 a v in = 0 v table 5.6 dc characteristics (5) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions supply current* 1 high-speed operating mode normal operating mode no peripheral operation* 2 iclk = 50 mhz i cc 10 ? ma all peripheral operation: normal* 3 iclk = 50 mhz 31.5 ? all peripheral operation: max.* 3 iclk = 50 mhz ? 55 sleep mode no peripheral operation iclk = 50 mhz 7.5 ? all peripheral operation: normal iclk = 50 mhz 17.5 ? all-module clock stop mode iclk = 50 mhz 6.7 ? increase during bgo operation* 4 25 ?
r01ds0041ej0150 rev.1.50 page 90 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version a] note 1. supply current values do not include output charge/disc harge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peri pheral functions is stopped. this does not include bgo operation. the clock source is pll and th e vco oscillation frequency is 64 mhz. bclk, fclk, and pclk are set to divided by 64. note 3. clock supply to the peri pheral functions is stopped. this does not include bgo operation. the clock source is hoco and t he oscillation frequency is 40 mhz. bclk, fclk, and pclk are set to divided by 64. note 4. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is pll and the vc o oscillation frequency is 64 mhz. bclk, fclk, and pclk are iclk divided by 1. table 5.7 dc characteristics (6) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions supply current* 1 middle-speed operating modes 1a and 1b normal operating mode no peripheral operation iclk = 32 mhz* 2 i cc 7.0 ? ma iclk = 20 mhz* 3 6.0 ? all peripheral operation: normal iclk = 32 mhz* 4 26 ? iclk = 20 mhz* 5 18.5 ? all peripheral operation: max. iclk = 32 mhz* 4 ?40 iclk = 20 mhz* 5 ?30 sleep mode no peripheral operation iclk = 32 mhz 5.0 ? iclk = 20 mhz 4.6 ? all peripheral operation: normal iclk = 32 mhz 15.5 ? iclk = 20 mhz 12 ? all-module clock stop mode iclk = 32 mhz 4.5 ? iclk = 20 mhz 4.3 ? increase during bgo operation* 6 middle-speed operating mode 1a 25 ? middle-speed operating mode 1b 20 ? low-speed operating mode 1 normal operating mode no peripheral operation* 7 iclk = 1 mhz 0.68 ? all peripheral operation: normal* 8 iclk = 1 mhz 2.4 ? all peripheral operation: max.* 8 iclk = 1 mhz ? 7 sleep mode no peripheral operation iclk = 1 mhz 0.6 ? all peripheral operation: normal iclk = 1 mhz 2 ? all-module clock stop mode 0.58 ? low-speed operating mode 2 normal operating mode no peripheral operation* 9 iclk = 32 khz 0.024 ? all peripheral operation: normal* 10 iclk = 32 khz 0.05 ? all peripheral operation: max.* 10 iclk = 32 khz ? 3* 11 sleep mode no peripheral operation iclk = 32 khz 0.02 ? all peripheral operation: normal iclk = 32 khz 0.04 ? all-module clock stop mode 0.018 ?
r01ds0041ej0150 rev.1.50 page 91 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note 5. clocks are supplied to the peripheral functions. this does not include bgo oper ation. the clock source is hoco and the oscillation frequency is 40 mhz. bclk, fclk, and pclk are iclk divided by 1. note 6. this is the increase if data is programmed to or er asing from the rom or e2 dataflash during program execution. note 7. clock supply to the peri pheral functions is stopped. this does not include bgo operation. the clock source is hoco and t he oscillation frequency is 32 mhz. bclk, fclk, and pclk are set to divided by 64. note 8. clocks are supplied to the peripheral functions. this does not include bgo oper ation. the clock source is hoco and the oscillation frequency is 32 mhz. bclk, fclk, and pclk are iclk divided by 1. note 9. clock supply to the peri pheral functions is stopped. this does not include bgo operation. the clock source is the sub os cillation circuit. bclk, fclk, and pclk are set to divided by 64. note 10. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is the sub oscil lation circuit. bclk, fclk, and pclk are iclk divided by 1. note 11. value when the main clock continues oscillat ing at 12.5 mhz.
r01ds0041ej0150 rev.1.50 page 92 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.1 voltage dependency in high-speed operating mode (reference data) for chip version a figure 5.2 voltage dependency in middle-speed op erating modes 1a and 1b (reference data) for chip version a vcc (v) 0 5 10 15 20 25 30 35 2.5 3 3.5 4 4.5 5 5.5 6 icc (ma) 40 ta = 105c, iclk = 50 mhz* 2 ta = 25c, iclk = 50 mhz* 1 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. vcc (v) 0 5 10 15 20 25 30 35 2.5 3 3.5 4 4.5 5 5.5 6 icc (ma) ta = 25c, iclk = 20 mhz* 1 ta = 25c, iclk = 32 mhz* 1 ta = 105c, iclk = 20 mhz* 2 ta = 105c, iclk = 32 mhz* 2 1.5 2 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 93 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.3 voltage dependency in low-speed operating mode 1 (reference data) for chip version a figure 5.4 voltage dependency in low-speed operating mode 2 (reference data) for chip version a 0 0.5 1 1.5 2 2.5 3 3.5 icc (ma) 4 2.53 3.54 4.555.56 1.5 2 ta = 105c, iclk = 1 mhz* 2 ta=25c, iclk=1mhz* 1 vcc (v) note 1. all peripheral operation is normal. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. average value of the tested upper-limit samples during product evaluation. ta = 105c, iclk = 32 khz* 2 ta=25c, iclk=32khz* 1 0 20 40 60 80 100 120 140 160 180 2.53 3.54 4.555.56 1.5 2 icc (a) vcc (v) note 1. all peripheral operation is normal. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 94 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version a] note 1. supply current values are with all output pins unloaded and all input pull- up moss in the off state. note 2. the iwdt and lvd are stopped. note 3. vcc = 3.3 v. table 5.8 dc characteristics (7) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = 0 v, t a = ?40 to +105c item symbol typ.* 3 max. unit test conditions supply current* 1 software standby mode* 2 flash memory power supplied, hoco power supplied, por low power consumption function disabled (softcut[2:0] bits = 000b) t a = 25c i cc 175 ? a flash memory power supplied, hoco power not supplied, por low power consumption function enabled (softcut[2:0] bits = 110b) t a = 25c 3.0 ? t a = 85c ? 130 t a = 105c ? 150 flash memory power not supplied, hoco power not supplied, por low power consumption function enabled (softcut[2:0] bits = 111b) t a = 25c 2.0 ? t a = 85c ? 120 t a = 105c ? 140 deep software standby mode* 2 flash memory power not supplied, hoco power not supplied, por low power consumption function enabled (deepcut1 bit = 1) t a = 25c 0.45 t a = 85c ? 20 t a = 105c ? 25 increments produced by running voltage detection circuits and disabling the por low power consumption function 1.4 ? increment for rtc operation (low cl) 0.8 ? increment for rtc operation (standard cl) 2.0 ?
r01ds0041ej0150 rev.1.50 page 95 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.5 voltage dependency in software standby mode (softcut[2:0] bits = 111b) (reference data) for chip version a figure 5.6 temperature dependency in software standby mode (softcut[2:0] bits = 111b) (reference data) for chip version a vcc (v) 1.00 10.00 icc (a) 100.00 2.5 3.5 4.5 5.5 1.5 ta = 25c* 2 ta = 55c* 1 ta = 105c* 2 ta = 85c* 2 ta = 105c* 1 ta = 55c* 2 ta = 85c* 1 ta = 25c* 1 note 1. average value of the tested mi ddle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. 1.00 10.00 100.00 -40 -20 0 20 40 60 80 100 ta (c) icc (a) vcc = 3.3 v* 2 vcc = 3.3 v* 1 note 1. average value of the tested mi ddle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 96 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.7 voltage dependency in deep software standby mode (deepcut1 bit = 1) (reference data) for chip version a figure 5.8 temperature dependency in deep software standby m ode (deepcut1 bit = 1) (reference data) for chip version a 1.5 vcc (v) 2.5 3 3.5 4 4.5 5 5.5 6 2 0.10 1.00 icc (a) 10.00 ta = 105c* 2 ta = 85c* 1 ta = 55c* 2 ta = 105c* 1 ta = 85c* 2 ta = 55c* 1 ta = 25c* 2 ta = 25c* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. 0.10 1.00 10.00 -40 -20 0 20 40 60 80 100 ta (c) icc (a) vcc = 3.3 v* 2 vcc = 3.3 v* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 97 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version c] note 1. supply current values do not include output charge/disc harge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peripheral functions is stopped. this does not include bgo operation. the clock source is pll and th e vco oscillation frequency is 100 mhz. bclk, fclk, and pclk are set to divided by 64. note 3. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is pll and the vc o oscillation frequency is 100 mhz. bclk, fclk, and pclk are iclk divided by 2. note 4. this is the increase if data is programmed to or er asing from the rom or e2 dataflash during program execution. table 5.9 dc characteristics (8) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions supply current* 1 high-speed operating mode normal operating mode no peripheral operation* 2 iclk = 50 mhz i cc 10 ? ma all peripheral operation: normal* 3 iclk = 50 mhz 31.5 ? all peripheral operation: max.* 3 iclk = 50 mhz ? 55 sleep mode no peripheral operation iclk = 50 mhz 7.5 ? all peripheral operation: normal iclk = 50 mhz 17.5 ? all-module clock stop mode iclk = 50 mhz 6.7 ? increase during bgo operation* 4 25 ?
r01ds0041ej0150 rev.1.50 page 98 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version c] table 5.10 dc characteristics (9) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c note 1. supply current values do not include output charge/disc harge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peripheral functions is stopped. this does not include bgo operation. the clock source is pll and th e vco oscillation frequency is 64 mhz. bclk, fclk, and pclk are set to divided by 64. note 3. clock supply to the peripheral func tions is stopped. this does not include bgo operation. the clock source is hoco and t he oscillation frequency is 40 mhz. bclk, fclk, and pclk are set to divided by 64. note 4. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is pll and the vc o oscillation frequency is 64 mhz. bclk, fclk, and pclk are iclk divided by 1. item symbol typ. max. unit test conditions supply current* 1 middle-speed operating modes 1a and 1b normal operating mode no peripheral operation iclk = 32 mhz* 2 i cc 7.0 ? ma iclk = 20 mhz* 3 6.0 ? all peripheral operation: normal iclk = 32 mhz* 4 26 ? iclk = 20 mhz* 5 18.5 ? all peripheral operation: max. iclk = 32 mhz* 4 ?40 iclk = 20 mhz* 5 ?30 sleep mode no peripheral operation iclk = 32 mhz 5.0 ? iclk = 20 mhz 4.6 ? all peripheral operation: normal iclk = 32 mhz 15.5 ? iclk = 20 mhz 12 ? all-module clock stop mode iclk = 32 mhz 4.5 ? iclk = 20 mhz 4.5 ? increase during bgo operation* 6 middle-speed operating mode 1a 25 ? middle-speed operating mode 1b 20 ? low-speed operating mode 1 normal operating mode no peripheral operation* 7 iclk = 1 mhz 0.68 ? all peripheral operation: normal* 8 iclk = 1 mhz 2.4 ? all peripheral operation: max. * 8 iclk = 1 mhz ? 7 sleep mode no peripheral operation iclk = 1 mhz 0.6 ? all peripheral operation: normal iclk = 1 mhz 2 ? all-module clock stop mode 0.58 ? low-speed operating mode 2 normal operating mode no peripheral operation* 9 iclk = 32 khz 0.024 ? all peripheral operation: normal* 10 iclk = 32 khz 0.05 ? all peripheral operation: max. * 10 iclk = 32 khz ? 3* 11 sleep mode no peripheral operation iclk = 32 khz 0.02 ? all peripheral operation: normal iclk = 32 khz 0.04 ? all-module clock stop mode 0.018 ?
r01ds0041ej0150 rev.1.50 page 99 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note 5. clocks are supplied to the peripheral functions. this does not include bgo oper ation. the clock source is hoco and the oscillation frequency is 40 mhz. bclk, fclk, and pclk are iclk divided by 1. note 6. this is the increase if data is programmed to or er asing from the rom or e2 dataflash during program execution. note 7. clock supply to the peripheral func tions is stopped. this does not include bgo operation. the clock source is hoco and t he oscillation frequency is 32 mhz. bclk, fclk, and pclk are set to divided by 64. note 8. clocks are supplied to the peripheral functions. this does not include bgo oper ation. the clock source is hoco and the oscillation frequency is 32 mhz. bclk, fclk, and pclk are iclk divided by 1. note 9. clock supply to the peri pheral functions is stopped. this does not include bgo operation. the clock source is the sub os cillation circuit. bclk, fclk, and pclk are set to divided by 64. note 10. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is the sub oscil lation circuit. bclk, fclk, and pclk are iclk divided by 1. note 11. value when the main clock continues oscillating at 12.5 mhz.
r01ds0041ej0150 rev.1.50 page 100 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.9 voltage dependency in high-speed operating mode (reference data) for chip version c figure 5.10 voltage dependency in middle-speed op erating modes 1a and 1b (reference data) for chip version c vcc (v) 0 5 10 15 20 25 30 35 2.5 3 3.5 4 4.5 5 5.5 6 icc (ma) 40 ta = 105c, iclk = 50 mhz* 2 ta = 25c, iclk = 50 mhz* 1 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. vcc (v) 0 5 10 15 20 25 30 35 2.5 3 3.5 4 4.5 5 5.5 6 icc (ma) ta = 25c, iclk = 20 mhz* 1 ta = 25c, iclk = 32 mhz* 1 ta = 105c, iclk = 20 mhz* 2 ta = 105c, iclk = 32 mhz* 2 1.5 2 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 101 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.11 voltage dependency in low-speed operating mode 1 (reference data) for chip version c figure 5.12 voltage dependency in low-speed operating mode 2 (reference data) for chip version c 0 0.5 1 1.5 2 2.5 3 3.5 icc (ma) 4 2.5 3 3.5 4 4.5 5 5.5 6 1.5 2 ta = 105c, iclk = 1 mhz* 2 ta = 25c, iclk = 1 mhz* 1 vcc (v) note 1. all peripheral operation is normal. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. average value of the tested upper-limit samples during product evaluation. ta = 105c, iclk = 32 khz* 2 ta=25c, iclk=32khz* 1 0 20 40 60 80 100 120 140 160 180 2.53 3.54 4.555.56 1.5 2 icc (a) vcc (v) note 1. all peripheral operation is normal. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 102 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version c] note 1. supply current values are with all output pins unloaded and all input pull-up moss in the off state. note 2. the iwdt and lvd are stopped. note 3. vcc = 3.3 v. table 5.11 dc characteristics (10) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = 0 v, t a = ?40 to +105c item symbol typ.* 3 max. unit test conditions supply current* 1 software standby mode* 2 flash memory power supplied, hoco power supplied, por low power consumption function disabled (softcut[2:0] bits = 000b) t a = 25c i cc 160 ? a t a = 55c 188 ? t a = 85c 220 ? t a = 105c 250 ? flash memory power supplied, hoco power not supplied, por low power consumption function enabled (softcut[2:0] bits = 110b) t a = 25c 2.6 10.5 t a = 55c 3.8 22 t a = 85c 9.0 80 t a = 105c 20 150 flash memory power not supplied, hoco power not supplied, por low power consumption function enabled (softcut[2:0] bits = 111b) t a = 25c 2.0 8.2 t a = 55c 2.9 17 t a = 85c 6.8 53 t a = 105c 15 115 deep software standby mode* 2 flash memory power not supplied, hoco power not supplied, por low power consumption function enabled (deepcut1 bit = 1) t a = 25c 0.5 0.9 t a = 55c 0.6 1.2 t a = 85c 0.9 20 t a = 105c 1.8 25 increments produced by running voltage detection circuits and disabling the por low power consumption function 1.4 ? increment for rtc operation (low cl) 0.8 ? increment for rtc operation (standard cl) 2.0 ?
r01ds0041ej0150 rev.1.50 page 103 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.13 voltage dependency in software standby mode (softcut[2:0] bits = 111b) (reference data) for chip version c figure 5.14 temperature dependency in software standby mode (softcut[2:0] bits = 111b) (reference data) for chip version c vcc (v) 1.00 10.00 icc (a) 100.00 2.5 3.5 4.5 5.5 1.5 ta = 25c* 2 ta = 55c* 1 ta = 105c* 2 ta = 85c* 2 ta = 105c* 1 ta = 55c* 2 ta = 85c* 1 ta = 25c* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. 1.00 10.00 100.00 -40 -20 0 20 40 60 80 100 ta (c) icc (a) vcc = 3.3 v* 2 vcc = 3.3 v* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 104 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.15 voltage dependency in deep software standby mode (deepcut1 bit = 1) (reference data) for chip version c figure 5.16 temperature dependency in deep software sta ndby mode (deepcut1 bit = 1) (reference data) for chip version c 1.5 vcc (v) 2.5 3 3.5 4 4.5 5 5.5 6 2 0.10 1.00 icc (a) 10.00 ta = 105c* 2 ta = 85c* 1 ta = 55c* 2 ta = 105c* 1 ta = 85c* 2 ta = 55c* 1 ta = 25c* 2 ta = 25c* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. 0.10 1.00 10.00 -40 -20 0 20 40 60 80 100 ta (c) icc (a) vcc = 3.3 v* 2 vcc = 3.3 v* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 105 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b with 256 kbytes or less of flash memory and 48 to 100 pins] note 1. supply current values do not include output charge/disc harge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peripheral functions is stopped. this does not include bgo operation. the clock source is pll and th e vco oscillation frequency is 100 mhz. bclk, fclk, and pclk are set to divided by 64. note 3. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is pll and the vc o oscillation frequency is 100 mhz. bclk, fclk, and pclk are iclk divided by 2. note 4. this is the increase if data is programmed to or er asing from the rom or e2 dataflash during program execution. table 5.12 dc characteristics (11) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions supply current* 1 high-speed operating mode normal operating mode no peripheral operation* 2 iclk = 50 mhz i cc 7.2 ? ma all peripheral operation: normal* 3 iclk = 50 mhz 23.5 ? all peripheral operation: max.* 3 iclk = 50 mhz ? 45 sleep mode no peripheral operation iclk = 50 mhz 4.3 ? all peripheral operation: normal iclk = 50 mhz 12 ? all-module clock stop mode iclk = 50 mhz 3.7 ? increase during bgo operation* 4 20 ?
r01ds0041ej0150 rev.1.50 page 106 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b with 256 kbytes or less of flash memory and 48 to 100 pins] table 5.13 dc characteristics (12) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions supply current* 1 middle-speed operating modes 1a and 1b normal operating mode no peripheral operation iclk = 32 mhz* 2 i cc 5.3 ? ma iclk = 20 mhz* 3 4.6 ? all peripheral operation: normal iclk = 32 mhz* 4 20.1 ? iclk = 20 mhz* 5 14.3 ? all peripheral operation: max. iclk = 32 mhz* 4 ?35 iclk = 20 mhz* 5 ?? sleep mode no peripheral operation iclk = 32 mhz 3.4 ? iclk = 20 mhz 3.3 ? all peripheral operation: normal iclk = 32 mhz 11.5 ? iclk = 20 mhz 9 ? all-module clock stop mode iclk = 32 mhz 3 ? iclk = 20 mhz 3 ? increase during bgo operation* 6 middle-speed operating mode 1a 17 ? middle-speed operating mode 1b 17 ? middle-speed operating modes 2a and 2b normal operating mode no peripheral operation* 2 iclk = 32 mhz 4.7 ? iclk = 16 mhz 3.4 ? iclk = 8 mhz 2.7 ? all peripheral operation: normal* 4 iclk = 32 mhz 19.6 ? iclk =16 mhz 11.3 ? iclk = 8 mhz 7.2 ? all peripheral operation: max.* 4 iclk = 32 mhz ? 34 iclk = 16 mhz ? ? iclk = 8 mhz ? ? sleep mode no peripheral operation iclk = 32 mhz 2.8 ? iclk = 16 mhz 2.5 ? iclk = 8 mhz 2.2 ? all peripheral operation: normal iclk = 32 mhz 11 ? iclk = 16 mhz 7.2 ? iclk = 8 mhz 5.3 ? all-module clock stop mode iclk = 32 mhz 2.4 ? iclk = 16 mhz 2.2 ? iclk = 8 mhz 2.1 ? increase during bgo operation* 6 middle-speed operating mode 1a 17 ? middle-speed operating mode 1b 17 ?
r01ds0041ej0150 rev.1.50 page 107 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note 1. supply current values do not include output charge/disc harge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peripheral functions is stopped. this does not include bgo operation. the clock source is pll and th e vco oscillation frequency is 64 mhz. bclk, fclk, and pclk are set to divided by 64. note 3. clock supply to the peripheral func tions is stopped. this does not include bgo operation. the clock source is hoco and t he oscillation frequency is 40 mhz. bclk, fclk, and pclk are set to divided by 64. note 4. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is pll and the vc o oscillation frequency is 64 mhz. bclk, fclk, and pclk are iclk divided by 1. note 5. clocks are supplied to the peripheral functions. this does not include bgo oper ation. the clock source is hoco and the oscillation frequency is 40 mhz. bclk, fclk, and pclk are iclk divided by 1. note 6. this is the increase if data is programmed to or er asing from the rom or e2 dataflash during program execution. note 7. clock supply to the peripheral func tions is stopped. this does not include bgo operation. the clock source is hoco and t he oscillation frequency is 32 mhz. bclk, fclk, and pclk are set to divided by 64. note 8. clocks are supplied to the peripheral functions. this does not include bgo oper ation. the clock source is hoco and the oscillation frequency is 32 mhz. bclk, fclk, and pclk are iclk divided by 1. note 9. clock supply to the peri pheral functions is stopped. this does not include bgo operation. the clock source is the sub os cillation circuit. bclk, fclk, and pclk are set to divided by 64. note 10. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is the sub oscil lation circuit. bclk, fclk, and pclk are iclk divided by 1. note 11. value when the main clock continues oscillating at 12.5 mhz. supply current* 1 low-speed operating mode 1 normal operating mode no peripheral operation* 7 iclk = 8 mhz i cc 2?ma iclk = 4 mhz 1.6 ? iclk = 2 mhz 1.5 ? all peripheral operation: normal* 8 iclk = 8 mhz 6 ? iclk = 4 mhz 3.8 ? iclk = 2 mhz 2.8 ? all peripheral operation: max.* 8 iclk = 8 mhz ? 12 iclk = 4 mhz ? ? iclk = 2 mhz ? ? sleep mode no peripheral operation iclk = 8 mhz 1.5 ? iclk = 4 mhz 1.4 ? iclk = 2 mhz 1.3 ? all peripheral operation: normal iclk = 8 mhz 3.6 ? iclk = 4 mhz 2.7 ? iclk = 2 mhz 2.2 ? all-module clock stop mode iclk = 8 mhz 1.4 ? iclk = 4 mhz 1.3 ? iclk = 2 mhz 1.2 ? low-speed operating mode 2 normal operating mode no peripheral operation* 9 iclk = 32 khz 0.021 ? all peripheral operation: normal* 10 iclk = 32 khz 0.05 ? all peripheral operation: max.* 10 iclk = 32 khz ? 3* 11 sleep mode no peripheral operation iclk = 32 khz 0.017 ? all peripheral operation: normal iclk = 32 khz 0.034 ? all-module clock stop mode 0.016 ? item symbol typ. max. unit test conditions
r01ds0041ej0150 rev.1.50 page 108 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.17 voltage dependency in high-speed operating mode (reference data) for chip version b with 256 kbytes or less of flash memory and 48 to 100 pins figure 5.18 voltage dependency in middle-speed op erating modes 1a and 1b (reference data) for chip version b with 256 kbytes or less of flash memory and 48 to 100 pins 0 5 10 15 20 25 30 35 2.5 3.5 4.5 5.5 vcc (v) icc (ma) ta = 105c, iclk = 50 mhz* 2 ta = 25c, iclk = 50 mhz* 1 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. vcc (v) 0 5 10 15 20 25 30 35 2.5 3.5 4.5 5.5 icc (ma) 1.5 ta = 105c, iclk = 32 mhz* 2 ta = 25c, iclk = 32 mhz* 1 ta = 105c, iclk = 20 mhz* 2 ta = 25c, iclk = 20 mhz* 1 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 109 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.19 voltage dependency in middle-speed op erating modes 2a and 2b (reference data) for chip version b with 256 kbytes or less of flash memory and 48 to 100 pins figure 5.20 voltage dependency in low-speed operating mode 1 (reference data) for chip version b with 256 kbytes or less of flash memory and 48 to 100 pins vcc (v) 0 5 10 15 20 25 30 35 2.5 3.5 4.5 5.5 icc (ma) 1.5 ta = 105c, iclk = 16 mhz* 2 ta = 25c, iclk = 16 mhz* 1 ta = 105c, iclk = 8 mhz* 2 ta = 25c, iclk = 8 mhz* 1 ta = 105c, iclk = 32 mhz* 2 ta = 25c, iclk = 32 mhz* 1 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. 2.5 3.5 4.5 5.5 1.5 vcc (v) 0 2 4 6 icc (ma) 8 ta = 105c, iclk = 8 mhz* 2 ta = 25c, iclk = 8 mhz* 1 ta = 105c, iclk = 2 mhz* 2 ta = 25c, iclk = 2 mhz* 1 ta = 105c, iclk = 4 mhz* 2 ta = 25c, iclk = 4 mhz* 1 note 1. all peripheral operation is normal. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 110 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.21 voltage dependency in low-speed operating mode 2 (reference data) for chip version b with 256 kbytes or less of flash memory and 48 to 100 pins vcc (v) 0 20 40 60 80 100 120 140 icc (a) 160 2.5 3.5 4.5 5.5 1.5 ta = 105c, iclk = 32 khz* 2 ta = 25c, iclk = 32 khz* 1 note 1. all peripheral operation is normal. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 111 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b with 256 kbytes or less of flash memory and 48 to 100 pins] note 1. supply current values are with all output pins unloaded and all input pull-up moss in the off state. note 2. the iwdt and lvd are stopped. note 3. vcc = 3.3 v. table 5.14 dc characteristics (13) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = 0 v, t a = ?40 to +105c item symbol typ.* 3 max. unit test conditions supply current* 1 software standby mode* 2 flash memory power supplied, hoco power supplied, por low power consumption function disabled (softcut[2:0] bits = 000b) t a = 25c i cc 10 18 a t a = 55c 13 35 t a = 85c 20 81 t a = 105c 34 154 flash memory power supplied, hoco power not supplied, por low power consumption function enabled (softcut[2:0] bits = 110b) t a = 25c 1.8 7.7 t a = 55c 3.3 20 t a = 85c 9.2 60 t a = 105c 20 124 deep software standby mode* 2 flash memory power not supplied, hoco power not supplied, por low power consumption function enabled (deepcut1 bit = 1) t a = 25c 0.4 0.8 t a = 55c 0.5 1.0 t a = 85c 0.7 2.5 t a = 105c 1.4 6.3 increments produced by running voltage detection circuits and disabling the por low power consumption function 1.4 ? increment for rtc operation (low cl) 0.8 ? increment for rtc operation (standard cl) 2.0 ?
r01ds0041ej0150 rev.1.50 page 112 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.22 voltage dependency in software standby mode (softcut[2:0] bits = 110b) (reference data) for chip version b with 256 kbytes or less of flash memory and 48 to 100 pins figure 5.23 temperature dependency in software standby mode (softcut[2:0] bits = 110b) (reference data) for chip version b with 256 kbytes or less of flash memory and 48 to 100 pins vcc (v) icc (a) 1.00 10.00 100.00 1.5 2.5 3 3.5 4 4.5 5 5.5 6 2 ta = 25c* 2 ta = 55c* 1 ta = 105c* 2 ta = 85c* 2 ta = 105c* 1 ta = 25c* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. ta = 55c* 2 ta = 85c* 1 10.00 100.00 -40 -20 0 20 40 60 80 100 ta (c) icc (a) 1.00 vcc = 3.3 v* 2 vcc = 3.3 v* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 113 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.24 voltage dependency in deep software standby mode (deepcut1 bit = 1) (reference data) for chip version b with 256 kbytes or less of flash memory and 48 to 100 pins figure 5.25 temperature dependency in deep software sta ndby mode (deepcut1 bit = 1) (reference data) for chip version b with 256 kbytes or less of flash memory and 48 to 100 pins note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. 1.5 vcc (v) 2.5 3 3.5 4 4.5 5 5.5 6 2 0.10 1.00 icc (a) 10.00 ta = 105c* 2 ta = 85c* 1 ta = 55c* 2 ta = 85c* 2 ta = 105c* 1 ta = 55c* 1 ta = 25c* 2 ta = 25c* 1 0.10 1.00 10.00 -40 -20 0 20 40 60 80 100 ta (c) icc (a) vcc = 3.3 v* 2 vcc = 3.3 v* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 114 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins] note 1. supply current values do not include output charge/disc harge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peripheral functions is stopped. this does not include bgo operation. the clock source is pll and th e vco oscillation frequency is 100 mhz. bclk, fclk, and pclk are set to divided by 64. note 3. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is pll and the vc o oscillation frequency is 100 mhz. bclk, fclk, and pclk are iclk divided by 2. note 4. this is the increase if data is programmed to or er asing from the rom or e2 dataflash during program execution. table 5.15 dc characteristics (14) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions supply current* 1 high-speed operating mode normal operating mode no peripheral operation* 2 iclk = 50 mhz i cc 7.8 ? ma all peripheral operation: normal* 3 iclk = 50 mhz 29.8 ? all peripheral operation: max.* 3 iclk = 50 mhz ? 45 sleep mode no peripheral operation iclk = 50 mhz 4.3 ? all peripheral operation: normal iclk = 50 mhz 13.5 ? all-module clock stop mode 3.7 ? increase during bgo operation* 4 23 ?
r01ds0041ej0150 rev.1.50 page 115 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins] table 5.16 dc characteristics (15) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions supply current* 1 middle-speed operating modes 1a and 1b normal operating mode no peripheral operation iclk = 32 mhz* 2 i cc 5.6 ? ma iclk = 20 mhz* 3 4.6 ? all peripheral operation: normal iclk = 32 mhz* 4 25.5 ? iclk = 20 mhz* 5 17.6 ? all peripheral operation: max. iclk = 32 mhz* 4 ?35 iclk = 20 mhz* 5 ?? sleep mode no peripheral operation iclk = 32 mhz 3.4 ? iclk = 20 mhz 3.3 ? all peripheral operation: normal iclk = 32 mhz 13.4 ? iclk = 20 mhz 10.2 ? all-module clock stop mode iclk = 32 mhz 3 ? iclk = 20 mhz 3 ? increase during bgo operation* 6 middle-speed operating mode 1a 23 ? middle-speed operating mode 1b 20 ? middle-speed operating modes 2a and 2b normal operating mode no peripheral operation* 2 iclk = 32 mhz 5.1 ? iclk = 16 mhz 3.5 ? iclk = 8 mhz 2.7 ? all peripheral operation: normal* 4 iclk = 32 mhz 25 ? iclk = 16 mhz 14 ? iclk = 8 mhz 8.5 ? all peripheral operation: max.* 4 iclk = 32 mhz ? 34 iclk = 16 mhz ? ? iclk = 8 mhz ? ? sleep mode no peripheral operation iclk = 32 mhz 2.9 ? iclk = 16 mhz 2.5 ? iclk = 8 mhz 2.2 ? all peripheral operation: normal iclk = 32 mhz 13 ? iclk = 16 mhz 8.2 ? iclk = 8 mhz 5.8 ? all-module clock stop mode iclk = 32 mhz 2.5 ? iclk = 16 mhz 2.2 ? iclk = 8 mhz 2.1 ? increase during bgo operation* 6 middle-speed operating mode 1a 23 ? middle-speed operating mode 1b 20 ?
r01ds0041ej0150 rev.1.50 page 116 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note 1. supply current values do not include output charge/disc harge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peripheral functions is stopped. this does not include bgo operation. the clock source is pll and th e vco oscillation frequency is 64 mhz. bclk, fclk, and pclk are set to divided by 64. note 3. clock supply to the peripheral func tions is stopped. this does not include bgo operation. the clock source is hoco and t he oscillation frequency is 40 mhz. bclk, fclk, and pclk are set to divided by 64. note 4. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is pll and the vc o oscillation frequency is 64 mhz. bclk, fclk, and pclk are iclk divided by 1. note 5. clocks are supplied to the peripheral functions. this does not include bgo oper ation. the clock source is hoco and the oscillation frequency is 40 mhz. bclk, fclk, and pclk are iclk divided by 1. note 6. this is the increase if data is programmed to or er asing from the rom or e2 dataflash during program execution. note 7. clock supply to the peripheral func tions is stopped. this does not include bgo operation. the clock source is hoco and t he oscillation frequency is 32 mhz. bclk, fclk, and pclk are set to divided by 64. note 8. clocks are supplied to the peripheral functions. this does not include bgo oper ation. the clock source is hoco and the oscillation frequency is 32 mhz. bclk, fclk, and pclk are iclk divided by 1. note 9. clock supply to the peri pheral functions is stopped. this does not include bgo operation. the clock source is the sub os cillation circuit. bclk, fclk, and pclk are set to divided by 64. note 10. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is the sub oscil lation circuit. bclk, fclk, and pclk are iclk divided by 1. note 11. value when the main clock continues oscillating at 12.5 mhz. supply current* 1 low-speed operating mode 1 normal operating mode no peripheral operation* 7 iclk = 8 mhz i cc 2.1 ? ma iclk = 4 mhz 1.7 ? iclk = 2 mhz 1.5 ? all peripheral operation: normal* 8 iclk = 8 mhz 7.3 ? iclk = 4 mhz 4.5 ? iclk = 2 mhz 3.1 ? all peripheral operation: max.* 7 iclk = 8 mhz ? 12 iclk = 4 mhz ? ? iclk = 2 mhz ? ? sleep mode no peripheral operation iclk = 8 mhz 1.5 ? iclk = 4 mhz 1.4 ? iclk = 2 mhz 1.3 ? all peripheral operation: normal iclk = 8 mhz 4.1 ? iclk = 4 mhz 3.0 ? iclk = 2 mhz 2.3 ? all-module clock stop mode iclk = 8 mhz 1.4 ? iclk = 4 mhz 1.3 ? iclk = 2 mhz 1.2 ? low-speed operating mode 2 normal operating mode no peripheral operation* 9 iclk = 32 khz 0.022 ? all peripheral operation: normal* 10 iclk = 32 khz 0.06 ? all peripheral operation: max.* 10 iclk = 32 khz ? 3* 11 sleep mode no peripheral operation iclk = 32 khz 0.017 ? all peripheral operation: normal iclk = 32 khz 0.036 ? all-module clock stop mode 0.017 ? item symbol typ. max. unit test conditions
r01ds0041ej0150 rev.1.50 page 117 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.26 voltage dependency in high-speed operating mode (reference data) for chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins figure 5.27 voltage dependency in middle-speed op erating modes 1a and 1b (reference data) for chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins vcc (v) icc (ma) note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. 0 5 10 15 20 25 30 35 2.5 3.5 4.5 5.5 ta = 105c, iclk = 50 mhz* 2 ta = 25c, iclk = 50 mhz* 1 0 5 10 15 20 25 30 35 2.5 3.5 4.5 5.5 1.5 vcc (v) icc (ma) ta = 105c, iclk = 32 mhz* 2 ta = 25c, iclk = 32 mhz* 1 ta = 105c, iclk = 20 mhz* 2 ta = 25c, iclk = 20 mhz* 1 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 118 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.28 voltage dependency in middle-speed op erating modes 2a and 2b (reference data) for chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins figure 5.29 voltage dependency in low-speed operating mode 1 (reference data) for chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins 0 5 10 15 20 25 30 35 2.5 3.5 4.5 5.5 1.5 vcc (v) icc (ma) ta = 105c, iclk = 16 mhz* 2 ta = 25c, iclk = 16 mhz* 1 ta = 105c, iclk = 32 mhz* 2 ta = 25c, iclk = 32 mhz* 1 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. ta = 105c, iclk = 8 mhz* 2 ta = 25c, iclk = 8 mhz* 1 2.5 3.5 4.5 5.5 1.5 0 2 4 6 8 10 vcc (v) icc (ma) ta = 105c, iclk = 8 mhz* 2 ta = 25c, iclk = 8 mhz* 1 ta = 105c, iclk = 2 mhz* 2 ta = 25c, iclk = 2 mhz* 1 ta = 105c, iclk = 4 mhz* 2 ta = 25c, iclk = 4 mhz* 1 note 1. all peripheral operation is normal. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 119 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.30 voltage dependency in low-speed operating mode 2 (reference data) for chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins 0 20 40 60 80 100 120 140 160 2.5 3.5 4.5 5.5 1.5 180 vcc (v) icc (a) ta = 105c, iclk = 32 khz* 2 ta = 25c, iclk = 32 khz* 1 note 1. all peripheral operation is normal. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 120 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins] note 1. supply current values are with all output pins unloaded and all input pull-up moss in the off state. note 2. the iwdt and lvd are stopped. note 3. vcc = 3.3 v. table 5.17 dc characteristics (16) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = 0 v, t a = ?40 to +105c item symbol typ.* 3 max. unit test conditions supply current* 1 software standby mode* 2 flash memory power supplied, hoco power supplied, por low power consumption function disabled (softcut[2:0] bits = 000b) t a = 25c i cc 10 34 a t a = 55c 13 87 t a = 85c 21 201 t a = 105c 40 352 flash memory power supplied, hoco power not supplied, por low power consumption function enabled (softcut[2:0] bits = 110b) t a = 25c 1.8 24 t a = 55c 3.3 70 t a = 85c 10 168 t a = 105c 25 302 deep software standby mode* 2 flash memory power not supplied, hoco power not supplied, por low power consumption function enabled (deepcut1 bit = 1) t a = 25c 0.4 0.8 t a = 55c 0.5 1.0 t a = 85c 0.7 2.5 t a = 105c 1.4 6.3 increments produced by running voltage detection circuits and disabling the por low power consumption function 1.4 ? increment for rtc operation (low cl) 0.8 ? increment for rtc operation (standard cl) 2.0 ?
r01ds0041ej0150 rev.1.50 page 121 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.31 voltage dependency in software standby mode (softcut[2:0] bits = 110b) (reference data) for chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins 1.00 10.00 100.00 1.5 2.5 3 3.5 4 4.5 5 5.5 6 2 1000.00 vcc (v) icc (a) ta = 55c* 1 ta = 105c* 2 ta = 85c* 2 ta = 55c* 2 ta = 25c* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. ta = 105c* 1 ta = 25c* 2 ta = 85c* 1
r01ds0041ej0150 rev.1.50 page 122 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.32 temperature dependency in software standby mode (softcut[2:0] bits = 110b) (reference data) for chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins 10.00 100.00 -40 -20 0 20 40 60 80 100 icc (a) 1.00 1000.00 vcc = 3.3 v* 2 vcc = 3.3 v* 1 ta (c) icc (a) note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 123 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.33 voltage dependency in deep software standby mode (deepcut1 bit = 1) (reference data) for chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins figure 5.34 temperature dependency in deep software sta ndby mode (deepcut1 bit = 1) (reference data) for chip version b with 768 kbytes/1 mbyte of flash memory and 100 to 145 pins 1.5 2.5 3 3.5 4 4.5 5 5.5 6 2 0.10 1.00 10.00 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. vcc (v) icc (a) ta = 105c* 2 ta = 85c* 1 ta = 55c* 2 ta = 85c* 2 ta = 105c* 1 ta = 55c* 1 ta = 25c* 2 ta = 25c* 1 0.10 1.00 10.00 -40 -20 0 20 40 60 80 100 ta (c) icc (a) vcc = 3.3 v* 2 vcc = 3.3 v* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 124 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b with 512 kbytes or less of flash memory and 144 and 145 pins] note 1. supply current values do not include output charge/disc harge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peripheral functions is stopped. this does not include bgo operation. the clock source is pll and th e vco oscillation frequency is 100 mhz. bclk, fclk, and pclk are set to divided by 64. note 3. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is pll and the vc o oscillation frequency is 100 mhz. bclk, fclk, and pclk are iclk divided by 2. note 4. this is the increase if data is programmed to or er asing from the rom or e2 dataflash during program execution. table 5.18 dc characteristics (17) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions supply current* 1 high-speed operating mode normal operating mode no peripheral operation* 2 iclk = 50 mhz i cc 7.2 ? ma all peripheral operation: normal* 3 iclk = 50 mhz 25.9 ? all peripheral operation: max.* 3 iclk = 50 mhz ? 45 sleep mode no peripheral operation iclk = 50 mhz 4.3 ? all peripheral operation: normal iclk = 50 mhz 13 ? all-module clock stop mode 3.7 ? increase during bgo operation* 4 21 ?
r01ds0041ej0150 rev.1.50 page 125 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b with 512 kbytes or less of flash memory and 144 and 145 pins] table 5.19 dc characteristics (18) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions supply current* 1 middle-speed operating modes 1a and 1b normal operating mode no peripheral operation iclk = 32 mhz* 2 i cc 5.3 ? ma iclk = 20 mhz* 3 4.6 ? all peripheral operation: normal iclk = 32 mhz* 4 22.3 ? iclk = 20 mhz* 5 15.6 ? all peripheral operation: max. iclk = 32 mhz* 4 ?35 iclk = 20 mhz* 5 ?? sleep mode no peripheral operation iclk = 32 mhz 3.4 ? iclk = 20 mhz 3.3 ? all peripheral operation: normal iclk = 32 mhz 12.8 ? iclk = 20 mhz 9.8 ? all-module clock stop mode iclk = 32 mhz 3 ? iclk = 20 mhz 3 ? increase during bgo operation* 6 middle-speed operating mode 1a 21 ? middle-speed operating mode 1b 19 ? middle-speed operating modes 2a and 2b normal operating mode no peripheral operation* 2 iclk = 32 mhz 4.7 ? iclk = 16 mhz 3.4 ? iclk = 8 mhz 2.7 ? all peripheral operation: normal* 4 iclk = 32 mhz* 3 21.7 ? iclk = 16 mhz* 3 12.3 ? iclk = 8 mhz 7.6 ? all peripheral operation: max.* 4 iclk = 32 mhz* 3 ?34 iclk = 16 mhz* 3 ?? iclk = 8 mhz ? ? sleep mode no peripheral operation iclk = 32 mhz 2.9 ? iclk = 16 mhz 2.5 ? iclk = 8 mhz 2.2 ? all peripheral operation: normal iclk = 32 mhz 12.3 ? iclk = 16 mhz 7.8 ? iclk = 8 mhz 5.6 ? all-module clock stop mode iclk = 32 mhz 2.5 ? iclk = 16 mhz 2.2 ? iclk = 8 mhz 2.1 ? increase during bgo operation* 6 middle-speed operating mode 1a 21 ? middle-speed operating mode 1b 19 ?
r01ds0041ej0150 rev.1.50 page 126 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note 1. supply current values do not include output charge/disc harge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peripheral functions is stopped. this does not include bgo operation. the clock source is pll and th e vco oscillation frequency is 64 mhz. bclk, fclk, and pclk are set to divided by 64. note 3. clock supply to the peripheral func tions is stopped. this does not include bgo operation. the clock source is hoco and t he oscillation frequency is 40 mhz. bclk, fclk, and pclk are set to divided by 64. note 4. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is pll and the vc o oscillation frequency is 64 mhz. bclk, fclk, and pclk are iclk divided by 1. note 5. clocks are supplied to the peripheral functions. this does not include bgo oper ation. the clock source is hoco and the oscillation frequency is 40 mhz. bclk, fclk, and pclk are iclk divided by 1. note 6. this is the increase if data is programmed to or er asing from the rom or e2 dataflash during program execution. note 7. clock supply to the peripheral func tions is stopped. this does not include bgo operation. the clock source is hoco and t he oscillation frequency is 32 mhz. bclk, fclk, and pclk are set to divided by 64. note 8. clocks are supplied to the peripheral functions. this does not include bgo oper ation. the clock source is hoco and the oscillation frequency is 32 mhz. bclk, fclk, and pclk are iclk divided by 1. note 9. clock supply to the peri pheral functions is stopped. this does not include bgo operation. the clock source is the sub os cillation circuit. bclk, fclk, and pclk are set to divided by 64. note 10. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is the sub oscil lation circuit. bclk, fclk, and pclk are iclk divided by 1. note 11. value when the main clock continues oscillating at 12.5 mhz. supply current* 1 low-speed operating mode 1 normal operating mode no peripheral operation* 7 iclk = 8 mhz i cc 2.0 ? ma iclk = 4 mhz 1.6 ? iclk = 2 mhz 1.5 ? all peripheral operation: normal* 8 iclk = 8 mhz 6.4 ? iclk = 4 mhz 4.0 ? iclk = 2 mhz 2.8 ? all peripheral operation: max.* 8 iclk = 8 mhz ? 12 iclk = 4 mhz ? ? iclk = 2 mhz ? ? sleep mode no peripheral operation iclk = 8 mhz 1.5 ? iclk = 4 mhz 1.4 ? iclk = 2 mhz 1.3 ? all peripheral operation: normal iclk = 8 mhz 3.9 ? iclk = 4 mhz 2.8 ? iclk = 2 mhz 2.2 ? all-module clock stop mode iclk = 8 mhz 1.4 ? iclk = 4 mhz 1.3 ? iclk = 2 mhz 1.2 ? low-speed operating mode 2 normal operating mode no peripheral operation* 9 iclk = 32 khz 0.021 ? all peripheral operation: normal* 10 iclk = 32 khz 0.06 ? all peripheral operation: max.* 10 iclk = 32 khz ? 3* 11 sleep mode no peripheral operation iclk = 32 khz 0.017 ? all peripheral operation: normal iclk = 32 khz 0.035 ? all-module clock stop mode 0.016 ? item symbol typ. max. unit test conditions
r01ds0041ej0150 rev.1.50 page 127 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.35 voltage dependency in high-speed operating mode (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins figure 5.36 voltage dependency in middle-speed op erating modes 1a and 1b (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. 0 5 10 15 20 25 30 35 2.5 3.5 4.5 5.5 vcc (v) icc (ma) ta = 105c, iclk = 50 mhz* 2 ta = 25c, iclk = 50 mhz* 1 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. vcc (v) 0 5 10 15 20 25 30 35 2.5 3.5 4.5 5.5 icc (ma) 1.5 ta = 105c, iclk = 32 mhz* 2 ta = 105c, iclk = 20 mhz* 2 ta = 25c, iclk = 32 mhz* 1 ta = 25c, iclk = 20 mhz* 1
r01ds0041ej0150 rev.1.50 page 128 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.37 voltage dependency in middle-speed op erating modes 2a and 2b (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins figure 5.38 voltage dependency in low-speed operating mode 1 (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. vcc (v) 0 5 10 15 20 25 30 35 2.5 3.5 4.5 5.5 icc (ma) 1.5 ta = 105c, iclk = 16 mhz* 2 ta = 25c, iclk = 16 mhz* 1 ta = 105c, iclk = 32 mhz* 2 ta = 105c, iclk = 8 mhz* 2 ta = 25c, iclk = 8 mhz* 1 ta = 25c, iclk = 32 mhz* 1 note 1. all peripheral operation is normal. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. average value of the tested upper-limit samples during product evaluation. 2.5 3.5 4.5 5.5 1.5 vcc (v) 0 2 4 6 icc (ma) 8 ta = 105c, iclk = 8 mhz* 2 ta = 25c, iclk = 8 mhz* 1 ta = 105c, iclk = 4 mhz* 2 ta = 25c, iclk = 4 mhz* 1 ta = 105c, iclk = 2 mhz* 2 ta = 25c, iclk = 2 mhz* 1 10
r01ds0041ej0150 rev.1.50 page 129 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.39 voltage dependency in low-speed operating mode 2 (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins note 1. all peripheral operation is normal. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. average value of the tested upper-limit samples during product evaluation. vcc (v) 0 20 40 60 80 100 120 140 icc (a) 160 2.5 3.5 4.5 5.5 1.5 ta = 105c, iclk = 32 khz* 2 ta = 25c, iclk = 32 khz* 1 180
r01ds0041ej0150 rev.1.50 page 130 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b with 512 kbytes or less of flash memory and 144 and 145 pins] note 1. supply current values are with all output pins unloaded and all input pull-up moss in the off state. note 2. the iwdt and lvd are stopped. note 3. vcc = 3.3 v. table 5.20 dc characteristics (19) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = 0 v, t a = ?40 to +105c item symbol typ.* 3 max. unit test conditions supply current* 1 software standby mode* 2 flash memory power supplied, hoco power supplied, por low power consumption function disabled (softcut[2:0] bits = 000b) t a = 25c i cc 10 18 a t a = 55c 13 52 t a = 85c 20 101 t a = 105c 34 173 flash memory power supplied, hoco power not supplied, por low power consumption function enabled (softcut[2:0] bits = 110b) t a = 25c 1.8 7.7 t a = 55c 3.3 30 t a = 85c 9.2 75 t a = 105c 20 139 deep software standby mode* 2 flash memory power not supplied, hoco power not supplied, por low power consumption function enabled (deepcut1 bit = 1) t a = 25c 0.4 0.8 t a = 55c 0.5 1.0 t a = 85c 0.7 2.5 t a = 105c 1.4 6.3 increments produced by running voltage detection circuits and disabling the por low power consumption function 1.4 ? increment for rtc operation (low cl) 0.8 ? increment for rtc operation (standard cl) 2.0 ?
r01ds0041ej0150 rev.1.50 page 131 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.40 voltage dependency in software standby mode (softcut[2:0] bits = 110b) (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. vcc (v) icc (a) 1.00 10.00 100.00 1.5 2.5 3 3.5 4 4.5 5 5.5 6 2 1000.00 ta = 105c* 2 ta = 55c* 1 ta = 85c* 2 ta = 55c* 2 ta = 105c* 1 ta = 25c* 2 ta = 85c* 1 ta = 25c* 1
r01ds0041ej0150 rev.1.50 page 132 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.41 temperature dependency in software standby mode (softcut[2:0] bits = 110b) (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. 10.00 100.00 -40 -20 0 20 40 60 80 100 ta (c) icc (a) vcc = 3.3 v* 2 vcc = 3.3 v* 1 1.00 1000.00
r01ds0041ej0150 rev.1.50 page 133 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.42 voltage dependency in deep software standby mode (deepcut1 bit = 1) (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins figure 5.43 temperature dependency in deep software sta ndby mode (deepcut1 bit = 1) (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins 1.5 2.5 3 3.5 4 4.5 5 5.5 6 2 0.10 1.00 10.00 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. vcc (v) icc (a) ta = 105c* 2 ta = 85c* 1 ta = 55c* 2 ta = 85c* 2 ta = 105c* 1 ta = 55c* 1 ta = 25c* 2 ta = 25c* 1 0.10 1.00 10.00 -40 -20 0 20 40 60 80 100 ta (c) icc (a) vcc = 3.3 v* 2 vcc = 3.3 v* 1 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation.
r01ds0041ej0150 rev.1.50 page 134 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note: ? please contact renesas electronics sales office for derat ing of operation under ta = +85c to +105c. derating is the systematic reduction of load for th e sake of improved reliability. note 1. total power dissipated by the entire chip (including output currents) note: ? the values for a/d conversion apply when the sample and hold circuit is not in use. note 1. the reference power supply current is included in the power supply current value for d/a conversion. note 2. the value is the total value of i avcc0 and i vrefh . table 5.21 dc characteristics (20) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions permissible total consumption power* 1 pd ? 350 mw ta = ?40 to 85c ? 150 85c < ta 105c table 5.22 dc characteristics (21) conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh = 1.8 to avcc0, vrefh0 = 1.62 to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions analog power supply current during a/d conversion i avcc0 ? 1.0 3.2 ma temperature sensor operating, waiting for a/d conversion ? 60 200 a during d/a conversion (per channel) i vrefh * 1 ? 0.25 0.75 ma waiting for a/d, d/a conversion (all units)* 2 ??0.25.0a reference power supply current during a/d conversion i vrefh0 ? 0.1 0.2 ma waiting for a/d conversion ? 0.2 0.4 a table 5.23 dc characteristics (22) conditions: vcc = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions ram standby voltage v ram 1.62 ? ? v table 5.24 dc characteristics (23) conditions: vcc = avcc0 = 0 to 5.5 v, vrefh = vrefh0 = 0 to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions vcc rising gradient srvcc 0.02 ? 20 ms/v at cold start
r01ds0041ej0150 rev.1.50 page 135 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.44 ripple waveform table 5.25 dc characteristics (24) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c the ripple voltage must meet the allowable ripple frequency f r(vcc) within the range between the vcc upper limit (5.5 v) and lower limit (1.62 v). when vcc change exceeds vcc 10%, the allowable voltage change rising/falling gradient dt/dvcc must be met. item symbol min. typ. max. unit test conditions allowable ripple frequency f r(vcc) ? ? 10 khz figure 5.44 vcc 0.1 < v r(vcc) vcc 0.2 ? ? 1 mhz figure 5.44 vcc 0.05 < v r(vcc) vcc 0.1 ? ? 10 mhz figure 5.44 v r(vcc) vcc 0.05 allowable voltage change rising/ falling gradient dt/dvcc 1.0 ? ? ms/v when vcc change exceeds vcc 10% table 5.26 permissible output currents (1) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, when total power (mw) < 1000 ? 10 ta item symbol max. unit permissible output low current (average value per 1 pin) normal output mode i ol 4.0 ma high-drive output mode 8.0 permissible output low current (maximum value per 1 pin) normal output mode 4.0 ma high-drive output mode 8.0 permissible output low current (total) total of all output pins ? i ol 80 ma permissible output high current (average value per 1 pin) normal output mode i oh ?4.0 ma high-drive output mode ?8.0 permissible output high current (maximum value per 1 pin) normal output mode ?4.0 ma high-drive output mode ?8.0 permissible output high current (total) total of all output pins ? i oh ?80 ma v r(vcc) vcc 1/f r(vcc)
r01ds0041ej0150 rev.1.50 page 136 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version a] [chip version a] [chip versions b and c] table 5.27 permissible output currents (2) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = av ss0 = vrefl = vrefl0 = 0 v, when total power (mw) 1000 ? 10 ta item symbol max. unit permissible output low current (average value per 1 pin) normal output mode i ol 2.0 ma high-drive output mode 4.0 permissible output low current (maximum value per 1 pin) normal output mode 2.0 ma high-drive output mode 4.0 permissible output low current (total) total of all output pins ? i ol 40 ma permissible output high current (average value per 1 pin) normal output mode i oh ?2.0 ma high-drive output mode ?4.0 permissible output high current (maximum value per 1 pin) normal output mode ?2.0 ma high-drive output mode ?4.0 permissible output high current (total) total of all output pins ? i oh ?40 ma table 5.28 output valu es of voltage (1) conditions: vcc = avcc0 = 1.62 to 2.7 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions output low all output pins (other than riic) normal output mode v ol ?0.4vi ol = 0.5 ma high-drive output mode ? 0.4 i ol = 1.0 ma output high all output pins normal output mode v oh vcc ? 0.4 ? v i oh = ?0.5 ma high-drive output mode vcc ? 0.4 ? i oh = ?1.0 ma table 5.29 output valu es of voltage (2) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions vcc = 2.7 to 4.0 v vcc = 4.0 to 5.5 v output low all output pins (other than riic) normal output mode v ol ?1.0vi ol = 3.0 ma i ol = 4.0 ma high-drive output mode ?1.0 i ol = 5.0 ma i ol = 8.0 ma riic pins ? 0.4 i ol = 3.0 ma ?0.6 i ol = 6.0 ma output high all output pins normal output mode v oh vcc ? 1.0 ? v i oh = ? 3.0 ma i oh = ? 4.0 ma high-drive output mode vcc ? 1.0 ? i oh = ? 5.0 ma i oh = ? 8.0 ma table 5.30 output valu es of voltage (3) conditions: vcc = avcc0 = 1.62 to 2.7 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions output low all output pins (other than riic) normal output mode v ol ?0.3vi ol = 0.5 ma high-drive output mode ? 0.3 i ol = 1.0 ma output high all output pins normal output mode v oh vcc ? 0.3 ? v i oh = ?0.5 ma high-drive output mode vcc ? 0.3 ? i oh = ?1.0 ma
r01ds0041ej0150 rev.1.50 page 137 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip versions b and c] [chip versions b and c] 5.2.1 standard i/o pin outp ut characteristics (1) figure 5.45 to figure 5.49 show the characteristics wh en normal output is selected by the drive capacity control register. figure 5.45 voh/vol and ioh/iol voltage characteri stics at ta = 25c when normal output is selected (reference data) table 5.31 output valu es of voltage (4) conditions: vcc = avcc0 = 2.7 to 4.0 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions output low all output pins (other than riic) normal output mode v ol ?0.5vi ol = 1.0 ma high-drive output mode ? 0.5 i ol = 2.0 ma riic pins ? 0.4 i ol = 3.0 ma ?0.6 i ol = 6.0 ma output high all output pins normal output mode v oh vcc ? 0.5 ? v i oh = ?1.0 ma high-drive output mode vcc ? 0.5 ? i oh = ?2.0 ma table 5.32 output valu es of voltage (5) conditions: vcc = avcc0 = 4.0 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions output low all output pins (other than riic) normal output mode v ol ?0.8vi ol = 2.0 ma high-drive output mode ? 0.8 i ol = 4.0 ma riic pins ? 0.4 i ol = 3.0 ma ?0.6 i ol = 6.0 ma output high all output pins normal output mode v oh vcc ? 0.8 ? v i oh = ?2.0 ma high-drive output mode vcc ? 0.8 ? i oh = ?4.0 ma 01 2 3 4 5 6 ioh/iol vs voh/vol ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 voh/vol [v] ioh/iol [ma] vcc = 5.5 v vcc = 5.5 v vcc = 3.3 v vcc = 2.7 v vcc = 2.7 v vcc = 1.62 v vcc = 1.62 v vcc = 3.3 v
r01ds0041ej0150 rev.1.50 page 138 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.46 voh/vol and ioh/iol temperature characteristics at vcc = 1.62 v when normal output is selected (reference data) figure 5.47 voh/vol and ioh/iol temperature characteristics at vcc = 2.7 v when normal output is selected (reference data) ?4 ?3 ?2 ?1 0 1 2 3 4 0 0.5 1 1.5 2 ta = 105c ioh/iol vs voh/vol voh/vol [v] ioh/iol [ma] ta = 25c ta = ?40c ta = 105c ta = 25c ta = ?40c ta = 25c ta = ?40c ?15 ?10 ?5 0 5 10 15 ioh/iol vs voh/vol voh/vol [v] ioh/iol [ma] 2.5 0 0.5 1 1.5 2 3 ta = 105c ta = 105c ta = 25c ta = ?40c
r01ds0041ej0150 rev.1.50 page 139 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.48 voh/vol and ioh/iol temperature characteristics at vcc = 3.3 v when normal output is selected (reference data) figure 5.49 voh/vol and ioh/iol temperature characteristics at vcc = 5.5 v when normal output is selected (reference data) ioh/iol vs voh/vol voh/vol [v] ioh/iol [ma] 0 0.5 1 1.5 2 2.5 3 3.5 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 10 15 20 25 ta = 105c ta = 25c ta = ?40c ta = 105c ta = 25c ta = ?40c ioh/iol vs voh/vol voh/vol [v] ioh/iol [ma] 012345 6 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 ta = 25c ta = 105c ta = ?40c ta = 25c ta = ?40c ta = 105c
r01ds0041ej0150 rev.1.50 page 140 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.2.2 standard i/o pin outp ut characteristics (2) figure 5.50 to figure 5.54 show the characteristics when high-drive output is select ed by the drive capacity control register. figure 5.50 voh/vol and ioh/iol voltage characteri stics at ta = 25c when high-drive output is selected (reference data) figure 5.51 voh/vol and ioh/iol temperature characteristics at vcc = 1.62 v when high-drive output is selected (reference data) vcc = 5.5 v vcc = 3.3 v vcc = 2.7 v vcc = 2.7 v vcc = 1.62 v vcc = 1.62 v ioh/iol vs voh/vol voh/vol [v] ioh/iol [ma] ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 6 01 2 3 4 5 vcc = 5.5 v vcc = 3.3 v ioh/iol vs voh/vol voh/vol [v] ioh/iol [ma] 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 ?8 ?6 ?4 ?2 0 2 4 6 ta = 105c ta = 25c ta = ?40c ta = 105c ta = 25c ta = ?40c
r01ds0041ej0150 rev.1.50 page 141 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.52 voh/vol and ioh/iol temperature characteristics at vcc = 2.7 v when high-drive output is selected (reference data) figure 5.53 voh/vol and ioh/iol temperature characteristics at vcc = 3.3 v when high-drive output is selected (reference data) ioh/iol vs voh/vol voh/vol [v] ioh/iol [ma] ta = 105c ta = 25c ta = ?40c ta = 105c ta = 25c ta = ?40c 00 . 511 . 522 . 5 3 ?30 ?20 ?10 0 10 20 30 ioh/iol vs voh/vol voh/vol [v] ioh/iol [ma] ta = 105c ta = 25c ta = ?40c ta = 105c ta = 25c ta = ?40c 0 0.5 1 1.5 2 2.5 3 3.5 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40
r01ds0041ej0150 rev.1.50 page 142 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.54 voh/vol and ioh/iol temperature characteristics at vcc = 5.5 v when high-drive output is selected (reference data) ta = 105c ta = 25c ta = ?40c ta = ?40c ioh/iol vs voh/vol voh/vol [v] ioh/iol [ma] 01 2 3 4 5 6 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 ta = 25c ta = 105c
r01ds0041ej0150 rev.1.50 page 143 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.2.3 riic pin output characteristics figure 5.55 to figure 5.58 show the output characteristics of the riic pin. figure 5.55 vol and iol voltage characteristics of riic output pin at ta = 25c (reference data) figure 5.56 vol and iol temperature characteristics of riic output pin at vcc = 2.7 v (reference data) vcc = 5.5 v vcc = 3.3 v vcc = 2.7 v iol vs vol [v] vol [v] iol [ma] 0 10 20 30 40 50 60 70 012 3 456 iol vs vol [v] vol [v] iol [ma] ta = 105c ta = 25c ta = ?40c 0 5 10 15 20 25 0 0.5 1 1.5 2 2.5 3
r01ds0041ej0150 rev.1.50 page 144 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.57 vol and iol temperature characteristics of riic output pin at vcc = 3.3 v (reference data) figure 5.58 vol and iol temperature characteristics of riic output pin at vcc = 5.5 v (reference data) ta = 105c ta = 25c ta = ?40c iol vs vol [v] vol [v] iol [ma] 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 ta = 105c ta = 25c ta = ?40c iol vs vol [v] vol [v] iol [ma] 012345 6 0 10 20 30 40 50 60 70 80
r01ds0041ej0150 rev.1.50 page 145 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.3 ac characteristics [chip versions a, b, and c] note 1. the lower-limit frequency of fclk is 4 mhz during programming or erasing of the flash memory. note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. [chip versions a, b, and c] note 1. the vcc is 2.7 to 5.5 v and the lower-limit frequency of fc lk is 4 mhz during programming or erasing of the flash memory . note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. [chip versions a, b, and c] note 1. the vcc is 1.62 to 3.6 v and the lower-limit frequency of fclk is 4 mhz during programming or erasing of the flash memor y. note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. table 5.33 operation frequency value (high-speed operating mode) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 50 mhz flashif clock (fclk)* 1 32 peripheral module clock (pclkb) 32 peripheral module clock (pclkd)* 2 50 external bus clock (bclk) 25 bclk pin output 12.5 table 5.34 operation frequency value (middlespeed operating mode 1a) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 20 32 32 mhz flashif clock (fclk)* 1 20 32 32 peripheral module clock (pclkb) 20 32 32 peripheral module clock (pclkd)* 2 20 32 32 external bus clock (bclk) 12 16 25 bclk pin output 6 8 12.5 table 5.35 operation frequency value (middle-speed operating mode 1b) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 20 32 32 mhz flashif clock (fclk)* 1 20 32 32 peripheral module clock (pclkb) 20 32 32 peripheral module clock (pclkd)* 2 20 32 32 external bus clock (bclk) 12 16 25 bclk pin output 6 8 12.5
r01ds0041ej0150 rev.1.50 page 146 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b] note 1. the vcc is 2.7 to 5.5 v and the lower-limit frequency of fc lk is 4 mhz during programming or erasing of the flash memory . note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. [chip version b] note 1. the vcc is 1.62 to 3.6 v and the lower-limit frequency of fclk is 4 mhz during programming or erasing of the flash memor y. note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. [chip versions a and c] note 1. programming and erasing the flash memory is impossible. note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. table 5.36 operation frequency value (middle-speed operating mode 2a) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 81 63 2m h z flashif clock (fclk)* 1 81 63 2 peripheral module clock (pclkb) 8 16 32 peripheral module clock (pclkd)* 2 81 63 2 external bus clock (bclk) 8 16 25 bclk pin output 8 8 12.5 table 5.37 operation frequency value (middle-speed operating mode 2b) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 81 63 2m h z flashif clock (fclk)* 1 81 63 2 peripheral module clock (pclkb) 8 16 32 peripheral module clock (pclkd)* 2 81 63 2 external bus clock (bclk) 8 16 25 bclk pin output 8 8 12.5 table 5.38 operation frequency value (low-speed operating mode 1) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 111m h z flashif clock (fclk)* 1 111 peripheral module clock (pclkb) 1 1 1 peripheral module clock (pclkd)* 2 111 external bus clock (bclk) 1 1 1 bclk pin output 1 1 1
r01ds0041ej0150 rev.1.50 page 147 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b] note 1. programming and erasing the flash memory is impossible. note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. [chip versions a, b, and c] note 1. programming and erasing the flash memory is impossible. note 2. the a/d converter cannot be used. table 5.39 operation frequency value (low-speed operating mode 1) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 248m h z flashif clock (fclk)* 1 248 peripheral module clock (pclkb) 2 4 8 peripheral module clock (pclkd)* 2 248 external bus clock (bclk) 2 4 8 bclk pin output 2 4 8 table 5.40 operation frequency value (low-speed operating mode 2) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl=vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 32.768 32.768 32.768 khz flashif clock (fclk)* 1 32.768 32.768 32.768 peripheral module clock (pclkb) 32.768 32.768 32.768 peripheral module clock (pclkd)* 2 32.768 32.768 32.768 external bus clock (bclk) 32.768 32.768 32.768 bclk pin output 32.768 32.768 32.768
r01ds0041ej0150 rev.1.50 page 148 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.3.1 clock timing note 1. when the extal external clock inpu t is used with divided by 1 (sckcr.bck[3:0] bits = 0000b and bckcr.bclkdiv bit = 0) to output from the bclk pin, the above should be satisfied with a duty cycle of 45 to 55%. note 1. when the extal external clock inpu t is used with divided by 1 (sckcr.bck[3:0] bits = 0000b and bckcr.bclkdiv bit = 0) to output from the bclk pin, the above should be satisfied with a duty cycle of 45 to 55%. note: ? set high driving ability for the output port pin to be used for the bclk pin function. note 1. when the extal external clock inpu t is used with divided by 1 (sckcr.bck[3:0] bits = 0000b and bckcr.bclkdiv bit = 0) to output from the bclk pin, the above should be satisfied with a duty cycle of 45 to 55%. table 5.41 bclk timing (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, fbclk = up to 25 mhz (bclk pin output frequency = up to 12.5 mhz), t a = ?40 to +105c item symbol min. typ. max. unit test conditions bclk pin output cycle time t bcyc 80 ? ? ns figure 5.59 bclk pin output high pulse width* 1 t ch 20 ? ? ns bclk pin output low pulse width* 1 t cl 20 ? ? ns bclk pin output rising time t cr ? ? 15 ns bclk pin output falling time t cf ? ? 15 ns table 5.42 bclk timing (2) conditions: vcc = avcc0 = 1.8 to 2.7 v, vss = avss0 = vrefl = vrefl0 = 0 v, fbclk = up to 16 mhz (bclk pin output frequency= up to 8 mhz), t a = ?40 to +105c item symbol min. typ. max. unit test conditions bclk pin output cycle time t bcyc 125 ? ? ns figure 5.59 bclk pin output high pulse width* 1 t ch 30 ? ? ns bclk pin output low pulse width* 1 t cl 30 ? ? ns bclk pin output rising time t cr ? ? 25 ns bclk pin output falling time t cf ? ? 25 ns table 5.43 bclk timing (3) conditions: vcc = avcc0 = 1.62 to 1.8 v, vss = avss0 = vrefl=vrefl0 = 0 v, fbclk = up to 12 mhz (bclk pin output frequency = up to 6 mhz), t a = ?40 to +105c item symbol min. typ. max. unit test conditions bclk pin output cycle time t bcyc 166.6 ? ? ns figure 5.59 bclk pin output high pulse width* 1 t ch 42 ? ? ns bclk pin output low pulse width* 1 t cl 42 ? ? ns bclk pin output rising time t cr ? ? 35 ns bclk pin output falling time t cf ? ? 35 ns
r01ds0041ej0150 rev.1.50 page 149 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note 1. the time interval from the time p36 and p37 are c onfigured for input and the main clock oscillator stopping bit (mosccr.mostp) is set to 0 (operati ng) until the clock becomes available. table 5.44 clock timing conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions extal external clock input cycle time t excyc 50 ? ? ns figure 5.60 extal external clock input high pulse width t exh 20 ? ? ns extal external clock input low pulse width t exl 20 ? ? ns extal external clock rising time t exr ?? 5ns extal external clock falling time t exf ?? 5ns extal external clock input wait time* 1 t exwt 1??ms main clock oscillator oscillation frequency* 2 f main 1 ? 20 mhz main clock oscillation st abilization time (crystal)* 2 t mainosc ? 3 ? ms figure 5.61 main clock oscillation stabiliza tion time (ceramic resonator)* 2 t mainosc ?50 s main clock oscillation stabilization wait time (crystal)* 2 t mainoscwt ?6?ms main clock oscillation stabilizati on wait time (ceramic resonator)* 2 t mainoscwt ? 100 s loco clock cycle time t cyc 7.27 8 8.89 s loco clock oscillation frequency* 6 f loco 112.5 125 137.5 khz loco clock oscillation stabilization wait time t locowt ? ? 20 s figure 5.62 hoco clock oscillation frequency* 7 f hoco 31.680 32 32.320 mhz ta = 0 to 50c 36.495 36.864 37.233 39.600 40 40.400 49.500 50 50.500 31.520 32 32.480 ta = -40 to 105c 36.311 36.864 37.417 39.400 40 40.600 49.250 50 50.750 hoco clock oscillation stabilization time 1 t hoco1 ? ? 300 s figure 5.63 hoco clock oscillation stabilization time 2 t hoco2 ? ? 175 s figure 5.64 hoco clock oscillation stabilization wait time t hocowt ? ? 350 s figure 5.64 hoco clock power supply stabilization time t hocop ? ? 350 s figure 5.65 pll input frequency f pllin 4 ? 12.5 mhz pll circuit oscillation frequency f pll 50 ? 100 mhz pll clock oscillation stabilization time pll operation started after main clock oscillation has settled t pll1 ? ? 500 s figure 5.66 pll clock oscillation stabilization wait time t pllwt1 1.5 ? ? ms pll clock oscillation stabilization time* 4 pll operation started before main clock oscillation has settled t pll2 ?3.5* 3 ? ms figure 5.67 pll clock oscillation stabilization wait time* 4 t pllwt2 ?7?ms pll clock power supply stabilization time (for chip version b only) t pllpw ? ? 30 s figure 5.68 sub-clock oscillator oscillation frequency f sub ? 32.768 ? khz sub-clock oscillation stabilization time* 5 t subosc 2 ? ? s figure 5.69 sub-clock oscillation stabilization wait time* 5 t suboscwt 4??s
r01ds0041ej0150 rev.1.50 page 150 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note 2. when specifying the main clock oscill ator stabilization time, load the moscwtcr register with a stabilization time value that is greater than the resonator-vendor-recommended value. when determini ng the main lock oscillation stabilization wait time, allow an adequate margin (2 times is recommended) for th e main clock oscillation stabilization time. start using the main clock in the main cl ock oscillation stabilization wait time (t mainoscwt) after setting up the main clock oscillator for operation with the mosccr.mostp bit. the indicated value is a reference value that is measured for an 8 mhz resonator. note 3. sum of the main clock oscillation stabiliza tion time and the pll oscill ation stabilization time. note 4. the indicated value is a reference value that is measured for an 8 mhz resonator. note 5. when specifying the sub-clock oscillation stabilization time, load the soscwt cr register with the resonator-vendor- recommended stabilization time value minus 2 seconds. when determin ing the sub-clock oscillation st abilization wait time, allow an adequate margin (2 times is recommended) for the sub-clock os cillation stabilization time. star t using the sub-clock in the sub-clock oscillation st abilization wait time (tsuboscwt) after setting up the sub-clock oscillator for operation with the sosccr.sostp or rcr3.rtcen bit. note 6. there is no minimum or maximum value for 69-pin wlbga. note 7. characteristic value before mounting on the board for 69-pin wlbga.
r01ds0041ej0150 rev.1.50 page 151 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.59 bclk pin output timing figure 5.60 extal external clock input timing figure 5.61 main clock oscillation start timing figure 5.62 loco clock oscillation start timing t cf t ch t bcyc t cr t cl bclk pin output test conditions: voh = vcc 0.7, vol = vcc 0.3, ioh = ? 1.0 ma, iol = 1.0 ma, c = 30 pf t exh t excyc extal external clock input vcc 0.5 t exl t exr t exf main clock oscillator output mosccr.mostp t mainosc main clock t mainoscwt loco clock lococr.lcstp t locowt
r01ds0041ej0150 rev.1.50 page 152 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.63 hoco clock oscillation start timing (after reset is canceled by setting the ofs1.hocoen bit to 0) figure 5.64 hoco clock oscillation start timi ng (oscillation is st arted by setting the hococr.hcstp bit) figure 5.65 hoco po wer control timing res# internal reset hoco clock ofs1.hocoen t hoco1 t reswt hococr.hcstp t hocowt t hoco2 hoco clock hoco clock output internal power supply for hoco hocopcr.hocopcnt t hocop hococr.hcstp
r01ds0041ej0150 rev.1.50 page 153 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.66 pll clock oscillation start timing (pll is operated after main clock oscillation has settled) figure 5.67 pll clock oscillation start timing (pll is operated be fore main clock oscillation has settled) figure 5.68 pll powe r control timing pllcr2.pllen pll clock mosccr.mostp t mainosc main clock oscillator output pll circuit output t pll1 t pllwt1 mosccr.mostp pll circuit output pllcr2.pllen t pll2 t mainosc main clock oscillator output pll clock t pllwt2 internal power supply for pll pllpcr.pllpcnt t pllpw pllcr2.pllen
r01ds0041ej0150 rev.1.50 page 154 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.69 sub-clock oscillation start timing sub-clock oscillator output sosccr.sostp t subosc sub-clock t suboscwt
r01ds0041ej0150 rev.1.50 page 155 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.3.2 reset timing figure 5.70 reset input timing at power-on figure 5.71 reset input timing table 5.45 reset timing conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions res# pulse width power-on t reswp 8 ? ? ms figure 5.70 deep software standby mode t reswd 8 ? ? ms figure 5.71 software standby mode, low-speed operating modes 1 and 2 t resws 1??ms programming or erasure of the rom or e2 dataflash memory or blank checking of the e2 dataflash memory t reswf 200 ? ? s other than above t resw 200 ? ? s wait time after res# cancellation t reswt ? ? 912 s figure 5.70 internal reset time (independent watchdog timer reset, watchdog timer reset, software reset) t resw2 ??1.4ms vcc res# t reswp internal reset t reswt 1.55 v res# internal reset t reswt t reswd, t resws, t reswf, t resw
r01ds0041ej0150 rev.1.50 page 156 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.3.3 timing of recovery from low power consumption modes [chip versions a and c] note 1. the recovery time varies depending on the state of each os cillator when the wait instruction is executed. the recovery t ime when multiple oscillators are operating varies depending on the oper ating state of the oscillators that are not selected as the system clock source, and depends on the time set in the wait control registers corresponding to the oscillators. note 2. the indicated value is measured for an 8 mhz crystal resonator. note 3. when rcr3.rtcen = 1, the time will be t he time set in the soscwtcr register minus 2 s. note 4. when rcr3.rtcen = 1, the time will be the time se t in the soscwtcr register minus 2 s and plus 31.25 ms. table 5.46 timing of recovery from low power consumption modes conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time after cancellation of software standby mode (flash memory, hoco power supplied) (softcut[2:0] bits = 000b)* 1 crystal resonator connected to main clock oscillator* 2 main clock oscillator operating t sbymc ? 3 ? ms figure 5.72 main clock oscillator and pll circuit operating t sbypc ?3.5?ms external clock input to main clock oscillator main clock oscillator operating t sbyex 10 ? ? s main clock oscillator and pll circuit operating t sbype 0.5 ? ? ms sub-clock oscillator operating t sbysc 2* 3 ??s hoco clock oscillator operating t sbyho ? ? 500 s loco clock oscillator operating t sbylo ??90s recovery time after cancellation of software standby mode (flash memory power supplied, hoco power not supplied) (softcut[2:0] bits = 110b)* 1 crystal resonator connected to main clock oscillator* 2 main clock oscillator operating t sbymc ? 3 ? ms figure 5.72 main clock oscillator and pll circuit operating t sbypc ?3.5?ms external clock input to main clock oscillator main clock oscillator operating t sbyex 40 ? ? s main clock oscillator and pll circuit operating t sbype 0.5 ? ? ms sub-clock oscillator operating t sbysc 2* 3 ??s hoco clock oscillator operating t sbyho ??1.2ms loco clock oscillator operating t sbylo ??90s recovery time after cancellation of software standby mode (flash memory, hoco power not supplied) (softcut[2:0] bits = 111b)* 1 crystal resonator connected to main clock oscillator* 2 main clock oscillator operating t sbymc ? 3 ? ms figure 5.72 main clock oscillator and pll circuit operating t sbypc ?3.5?ms external clock input to main clock oscillator main clock oscillator operating t sbyex 100 ? ? s main clock oscillator and pll circuit operating t sbype 0.5 ? ? ms sub-clock oscillator operating t sbysc 2* 4 ??s hoco clock oscillator operating t sbyho ??1.2ms loco clock oscillator operating t sbylo ??10ms recovery time after cancellation of deep software standby mode t dsby ? ? 8 ms figure 5.73 wait time after cancellation of deep software standby mode t dsbywt ??0.8ms
r01ds0041ej0150 rev.1.50 page 157 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b] note 1. the recovery time varies depending on the state of each os cillator when the wait instruction is executed. the recovery t ime when multiple oscillators are operating varies depending on the oper ating state of the oscillators that are not selected as the system clock source, and depends on the time set in the wait control registers corresponding to the oscillators. note 2. the indicated value is measured for an 8 mhz crystal resonator. note 3. when rcr3.rtcen = 1, the time will be t he time set in the soscwtcr register minus 2 s. table 5.47 timing of recovery from low power consumption modes conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time after cancellation of software standby mode (hoco power supplied) (softcut[2:0] bits = 000b)* 1 crystal resonator connected to main clock oscillator* 2 main clock oscillator operating t sbymc ? 3 ? ms figure 5.72 main clock oscillator and pll circuit operating t sbypc ?3.5?ms external clock input to main clock oscillator main clock oscillator operating t sbyex 10 ? ? s main clock oscillator and pll circuit operating t sbype 0.5 ? ? ms sub-clock oscillator operating t sbysc 2* 3 ??s hoco clock oscillator operating t sbyho ? ? 500 s loco clock oscillator operating t sbylo ??90s recovery time after cancellation of software standby mode (hoco power not supplied) (softcut[2:0] bits = 110b)* 1 crystal resonator connected to main clock oscillator* 2 main clock oscillator operating t sbymc ? 3 ? ms figure 5.72 main clock oscillator and pll circuit operating t sbypc ?3.5?ms external clock input to main clock oscillator main clock oscillator operating t sbyex 40 ? ? s main clock oscillator and pll circuit operating t sbype 0.5 ? ? ms sub-clock oscillator operating t sbysc 2* 3 ??s hoco clock oscillator operating t sbyho ??1.2ms loco clock oscillator operating t sbylo ??90s recovery time after cancellation of deep software standby mode t dsby ? ? 8 ms figure 5.73 wait time after cancellation of deep software standby mode t dsbywt ??0.8ms
r01ds0041ej0150 rev.1.50 page 158 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.72 software standby mode cancellation timing figure 5.73 deep software standby mode cancellation timing oscillator iclk irq software standby mode t sbymc, t sbypc, t sbyex, t sbype, t sbysc, t sbyho, t sbylo oscillator irq internal reset exceptional reset handling starts deep software standby mode deep software standby reset t dsby t dsbywt
r01ds0041ej0150 rev.1.50 page 159 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.3.4 control signal timing note: ? 200 ns minimum in deep software standby and software standby modes. figure 5.74 nmi interrupt input timing figure 5.75 irq interrupt input timing table 5.48 control signal timing conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions nmi pulse width t nmiw 200 ? ? ns t c(pclkb) 2 200 ns, figure 5.74 t c(pclkb) 2 ? ? ns t c(pclkb) 2 > 200 ns, figure 5.74 irq pulse width t irqw 200 ? ? ns t c(pclkb) 2 200 ns, figure 5.75 t c(pclkb) 2 ? ? ns t c(pclkb) 2 > 200 ns, figure 5.75 nmi t nmiw irq t irqw
r01ds0041ej0150 rev.1.50 page 160 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.3.5 bus timing table 5.49 bus timing (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, fbclk 25 mhz (bclk pin output frequency 12.5 mhz), t a = ?40 to +105c, v oh = vcc 0.5, v ol = vcc 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c l = 30 pf when normal output is selected by the drive capacity register item symbol min. max. unit test conditions address delay time t ad ? 60 ns figure 5.76 to figure 5.79 byte control delay time t bcd ?6 0n s cs# delay time t csd ?6 0n s rd# delay time t rsd ?6 0n s read data setup time t rds 40 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?6 0n s write data delay time t wdd ?6 0n s write data hold time t wdh 0?n s wait# setup time t wts 40 ? ns figure 5.80 wait# hold time t wth 0?n s table 5.50 bus timing (2) conditions: vcc = avcc0 = 1.8 to 2.7 v, vss = avss0 = vrefl = vrefl0 = 0 v, fbclk 16 mhz (bclk pin output frequency 8 mhz), t a = ?40 to +105c, v oh = vcc 0.5, v ol = vcc 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c l = 30 pf when normal output is selected by the drive capacity register item symbol min. max. unit test conditions address delay time t ad ? 90 ns figure 5.76 to figure 5.79 byte control delay time t bcd ?9 0n s cs# delay time t csd ?9 0n s rd# delay time t rsd ?9 0n s read data setup time t rds 60 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?9 0n s write data delay time t wdd ?9 0n s write data hold time t wdh 0?n s wait# setup time t wts 60 ? ns figure 5.80 wait# hold time t wth 0?n s
r01ds0041ej0150 rev.1.50 page 161 of 221 oct 18, 2013 rx210 group 5. electrical characteristics table 5.51 bus timing (3) conditions: vcc = avcc0 = 1.62 to 1.8 v, vss = avss0 = vrefl = vrefl0 = 0 v, fbclk 12 mhz (bclk pin output frequency 6 mhz), t a = ?40 to +105c, v oh = vcc 0.5, v ol = vcc 0.5, i oh = ?0.5 ma, i ol = 0.5 ma, c l = 30 pf when normal output is selected by the drive capacity register item symbol min. max. unit test conditions address delay time t ad ? 125 ns figure 5.76 to figure 5.79 byte control delay time t bcd ? 125 ns cs# delay time t csd ? 125 ns rd# delay time t rsd ? 125 ns read data setup time t rds 85 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ? 125 ns write data delay time t wdd ? 125 ns write data hold time t wdh 0?n s wait# setup time t wts 85 ? ns figure 5.80 wait# hold time t wth 0?n s
r01ds0041ej0150 rev.1.50 page 162 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.76 external bus timing/normal read cycle (bus clock synchronized) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 d15 to d0 (read) bus write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd rd# (read) t rsd t rsd t ad t rdh t rds t ad t ad t w1 t w2 t end t n1 t n2 rdon:1 csrwait:2 csroff:2 cson:0 t bcd t csd
r01ds0041ej0150 rev.1.50 page 163 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.77 external bus timing/normal write cycle (bus clock synchronized) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t ad t ad t ad d15 to d0 (write) wr1#, wr0#, wr# (write) t wrd t wrd t wdh t wdd t w1 t w2 t end t n1 t n2 wron:1 wdon:1 *1 cswwait:2 wdoff:1 *1 cson:0 note 1. set the values of wdon and wdoff to 1 or greater. t bcd t csd cswoff:2
r01ds0041ej0150 rev.1.50 page 164 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.78 external bus timing/page read cycle (bus clock synchronized) figure 5.79 external bus timing/page write cycle (bus clock synchronized) a23 to a1 cs3# to cs0# t ad bclk a23 to a0 d15 to d0 (read) byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd rd# (read) t rsd t rsd t rdh t rds t ad t w1 t w2 t end t pw1 t pw2 t ad t ad t rsd t rsd t rdh t rds t rsd t rsd t rdh t rds t end t pw1 t pw2 t end t n1 t n2 t ad t ad t ad t ad rdon:1 csrwait:2 csroff:2 t rsd t rsd t rdh t rds t ad t ad csprwait:2 t pw1 t pw2 t end rdon:1 csprwait:2 rdon:1 csprwait:2 rdon:1 cson:0 t bcd t csd a23 to a1 cs3# to cs0# t ad bclk a23 to a0 byte write strobe mode 1-write strobe mode bc1#, bc0# common to both byte write strobe mode and 1-write strobe mode t bcd t csd t ad t w1 d15 to d0 (write) wr1#, wr0#, wr# (write) t wrd t wrd t wdh t wdd t w2 t end t pw1 t pw2 t ad t ad t wrd t wrd t wdh t wdd t wrd t wrd t wdh t wdd t dw1 t end t pw1 t pw2 t end t n1 t n2 t dw1 t ad t ad t ad t ad wron:1 wdon:1 *1 cswwait:2 cspwwait:2 wdoff:1 *1 cspwwait:2 wdoff:1 *1 wdoff:1 *1 cson:0 wron:1 wdon:1 *1 wron:1 wdon:1 *1 note 1. set the values of wdon and wdoff to 1 or greater. t bcd t csd cswoff:2
r01ds0041ej0150 rev.1.50 page 165 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.80 external bus timing/external wait control t wts t wth t wts t wth csrwait:3 cswwait:3 bclk a23 to a0 cs3# to cs0# rd# (read) wr# (write) wait# t w1 t w2 (t end )t end t w3 t n1 t h external wait
r01ds0041ej0150 rev.1.50 page 166 of 221 oct 18, 2013 rx210 group 5. electrical characteristics table 5.52 bus timing (multiplexed bus) (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, fbclk 25 mhz (bclk pin output frequency 12.5 mhz), t a = ?40 to +105c, v oh = vcc 0.5, v ol = vcc 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c l = 30 pf when normal output is selected by the drive capacity register item symbol min. typ. max. unit address delay time t ad ? 60 ns figure 5.81 and figure 5.82 byte control delay time t bcd ?6 0n s cs# delay time t csd ?6 0n s rd# delay time t rsd ?6 0n s ale delay time t aled ?6 0n s read data setup time t rds 40 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?6 0n s write data delay time t wdd ?6 0n s write data hold time t wdh 0?n s wait# setup time t wts 40 ? ns figure 5.80 wait# hold time t wth 0?n s table 5.53 bus timing (multiplexed bus) (2) conditions: vcc = avcc0 = 1.8 to 2.7 v, vss = avss0 = vrefl = vrefl0 = 0 v, fbclk 16 mhz (bclk pin output frequency 8 mhz), t a = ?40 to +105c, v oh = vcc 0.5, v ol = vcc 0.5, i oh = ?1.0 ma, i ol = 1.0 ma, c l = 30 pf when normal output is selected by the drive capacity register item symbol min. typ. max. unit address delay time t ad ? 90 ns figure 5.81 and figure 5.82 byte control delay time t bcd ?9 0n s cs# delay time t csd ?9 0n s rd# delay time t rsd ?9 0n s ale delay time t aled ?9 0n s read data setup time t rds 60 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ?9 0n s write data delay time t wdd ?9 0n s write data hold time t wdh 0?n s wait# setup time t wts 60 ? ns figure 5.80 wait# hold time t wth 0?n s
r01ds0041ej0150 rev.1.50 page 167 of 221 oct 18, 2013 rx210 group 5. electrical characteristics table 5.54 bus timing (multiplexed bus) (3) conditions: vcc = avcc0 = 1.62 to 1.8 v, vss = avss0 = vrefl = vrefl0 = 0 v, fbclk 12 mhz (bclk pin output frequency 6 mhz), t a = ?40 to +105c, v oh = vcc 0.5, v ol = vcc 0.5, i oh = ?0.5 ma, i ol = 0.5 ma, c l = 30 pf when normal output is selected by the drive capacity register item symbol min. typ. max. unit address delay time t ad ? 125 ns figure 5.81 and figure 5.82 byte control delay time t bcd ? 125 ns cs# delay time t csd ? 125 ns rd# delay time t rsd ? 125 ns ale delay time t aled ? 125 ns read data setup time t rds 85 ? ns read data hold time t rdh 0?n s wr# delay time t wrd ? 125 ns write data delay time t wdd ? 125 ns write data hold time t wdh 0?n s wait# setup time t wts 85 ? ns figure 5.80 wait# hold time t wth 0?n s
r01ds0041ej0150 rev.1.50 page 168 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.81 example of operation in read access over the external bus (multiplexed) figure 5.82 example of operation in write access over the external bus (multiplexed) address/ data bus data read (rd#) t ad bclk address address latch (ale) chip select (cs3# to cs0#) t w1 t wn t ad t ad t su(db-rd) 40 ns (min) t end address cycle data cycle t aled t csd t csd t n1 t h 1 cycle fixed address cycle wait (await) t s(db-rd) 0 ns (min) t rsd t rss t rsd t rss read-access cs extension cycle (csroff) t aled rd assert wait (rdon) normal read cycle wait (csrwait) cs assert wait (cson) a d t rdh t rds t d(ad-ale) t h(ale-ad) address/ data bus data write (wr#) t ad bclk address address latch (ale) chip select (cs3# to cs0#) t w1 t ad t ad t end address cycle data cycle t csd t csd t n1 t h 1 cycle fixed t d(bclk-ale)= t aled address cycle wait (await) t rsd t rss t rsd t rss wr assert wait (wron) normal write cycle wait (csrwait) a d write data output wait (wdon) t d(bclk-ale)= t aled a read-access cs extension cycle (csroff)
r01ds0041ej0150 rev.1.50 page 169 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.3.6 timing of on-chi p peripheral modules note 1. t pcyc : pclk cycle note 2. t cac : cac count clock source cycle table 5.55 timing of on-chi p peripheral modules (1) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c when high-drive output is selected by the drive capacity register item symbol min. max. unit test conditions i/o ports input data pulse width t prw 1.5 ? t pcyc figure 5.83 mtu/ tpu input capture input pulse width single-edge setting t ticw 1.5 ? t pcyc figure 5.84 both-edge setting 2.5 ? timer clock pulse width single-edge setting t tckwh, t tckwl 1.5 ? t pcyc figure 5.85 both-edge setting 2.5 ? phase counting mode 2.5 ? poe poe# input pulse width t poew 1.5 ? t pcyc figure 5.86 8-bit timer timer clock pulse width single-edge setting t tmcwh, t tmcwl 1.5 ? t pcyc figure 5.87 both-edge setting 2.5 ? sci input clock cycle asynchronous t scyc 4?t pcyc figure 5.88 clock synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?2 0n s input clock fall time t sckf ?2 0n s output clock cycle asynchronous t scyc 16 ? t pcyc c = 30 pf figure 5.89 clock synchronous 4 ? output clock pulse width 2.7 v vcc 5.5 v t sckw 0.4 0.6 t scyc 1.8 v vcc < 2.7 v 0.35 0.65 1.62 v vcc < 1.8 v 0.35 0.65 output clock rise time t sckr ?2 0n s output clock fall time t sckf ?2 0n s transmit data delay time (master) clock synchronous t txd ?4 0n s transmit data delay time (slave) clock synchronous 2.7 v vcc 5.5 v ? 65 ns 1.8 v vcc < 2.7 v ? 85 ns 1.62 v vcc < 1.8 v ? 95 ns receive data setup time (master) clock synchronous 2.7 v vcc 5.5 v t rxs 65 ? ns 1.8 v vcc < 2.7 v 75 ? ns 1.62 v vcc < 1.8 v 80 ? ns receive data setup time (slave) clock synchronous 40 ? ns receive data hold time clock synchronous t rxh 40 ? ns a/d converter trigger input pulse width t trgw 1.5 ? t pcyc figure 5.90 cac cacref input pulse width t pcyc t cac * 2 t cacref 4.5 t cac + 3 t pcyc ?ns t pcyc > t cac * 2 5 t cac + 6.5 t pcyc
r01ds0041ej0150 rev.1.50 page 170 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [512 kbytes or less of flash memory and 48 to 100 pins] table 5.56 timing of on-chi p peripheral modules (2) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c when high-drive output is selected by the drive capacity register item symbol min. max. unit* 1 test conditions rspi rspck clock cycle master t spcyc 24 0 9 6t pcyc c = 30 pf figure 5.91 125 ? ns slave 8 4096 t pcyc rspck clock high pulse width master 2.7 v vcc 5.5 v t spckwh (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns 1.8 v vcc < 2.7 v (t spcyc ? t spckr ? t spckf )/2 ? 3 ? 1.62 v vcc < 1.8 v (t spcyc ? t spckr ? t spckf )/2 ? 10 ? slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock low pulse width master 2.7 v vcc 5.5 v t spckwl (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns 1.8 v vcc < 2.7 v (t spcyc ? t spckr ? t spckf )/2 ? 3 ? 1.62 v vcc < 1.8 v (t spcyc ? t spckr ? t spckf )/2 ? 10 ? slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock rise/fall time output 2.7 v vcc 5.5 v t spckr, t spckf ?1 0n s 1.8 v vcc < 2.7 v ? 15 1.62 v vcc < 1.8 v ? 20 input ? 1 s data input setup time master 2.7 v vcc 5.5 v t su 50 ? ns c = 30 pf figure 5.92 to figure 5.97 1.8 v vcc < 2.7 v 65 ? 1.62 v vcc < 1.8 v 75 ? slave 25 ? t pcyc ? data input hold time master t h t pcyc ?ns slave 20 + 2 t pcyc ? ssl setup time master t lead 18t spcyc slave 4 ? t pcyc ssl hold time master t lag 18t spcyc slave 4 ? t pcyc data output delay time master 2.7 v vcc 5.5 v t od ?5 0n s 1.8 v vcc < 2.7 v ? 55 1.62 v vcc < 1.8 v ? 60 slave 2.7 v vcc 5.5 v ? 3 t pcyc + 65 1.8 v vcc < 2.7 v ? 3 t pcyc + 85 1.62 v vcc < 1.8 v ? 3 t pcyc + 95 data output hold time master t oh 0?n s slave 0 ? successive transmission delay time master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 4 t pcyc ?
r01ds0041ej0150 rev.1.50 page 171 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note 1. t pcyc : pclk cycle [768 kbytes/1 mbyte of flash memory or 144/145 pins] item symbol min. max. unit* 1 test conditions rspi mosi and miso rise/ fall time output t dr, t df ?2 0n s c = 3 0 p f figure 5.92 to figure 5.97 input ? 1 s ssl rise/fall time output t sslr, t sslf ?2 0n s input ? 1 s slave access time 2.7 v vcc 5.5 v t sa ?6t pcyc c = 30 pf figure 5.96 and figure 5.97 1.8 v vcc < 2.7 v ? 7 1.62 v vcc < 1.8 v ? 7 slave output release time 2.7 v vcc 5.5 v t rel ?5t pcyc 1.8 v vcc < 2.7 v ? 6 1.62 v vcc < 1.8 v ? 6 table 5.57 timing of on-chi p peripheral modules (3) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c when high-drive output is selected by the drive capacity register item symbol min. max. unit* 1 test conditions rspi rspck clock cycle master t spcyc 24 0 9 6t pcyc c = 30pf figure 5.91 slave 8 4096 rspck clock high pulse width master 2.7 v vcc 5.5 v t spckwh (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns 1.8 v vcc < 2.7 v (t spcyc ? t spckr ? t spckf )/2 ? 3 ? 1.62 v vcc < 1.8 v (t spcyc ? t spckr ? t spckf )/2 ? 10 ? slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock low pulse width master 2.7 v vcc 5.5 v t spckwl (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns 1.8 v vcc < 2.7 v (t spcyc ? t spckr ? t spckf )/2 ? 3 ? 1.62 v vcc < 1.8 v (t spcyc ? t spckr ? t spckf )/2 ? 10 ? slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock rise/fall time output 2.7 v vcc 5.5 v t spckr, t spckf ?1 0n s 1.8 v vcc < 2.7 v ? 15 1.62 v vcc < 1.8 v ? 20 input ? 1 s
r01ds0041ej0150 rev.1.50 page 172 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note 1. t pcyc : pclk cycle note 2. divided by 2 can be set only in packages with 768 kbytes/1 mbyte of flash memory or 144/145 pins. item symbol min. max. unit* 1 test conditions rspi data input setup time master 2.7 v vcc 5.5 v t su 10 ? ns c = 30pf figure 5.92 to figure 5.97 1.8 v vcc < 2.7 v 25 ? 1.62 v vcc < 1.8 v 30 ? slave 25 ? t pcyc ? data input hold time master pclkb set to a division ratio other than divided by 2 t h t pcyc ?ns pclkb set to divided by 2* 2 t hf 0? slave t h 20 + 2 t pcyc ? ssl setup time master t lead 18t spcyc slave 4 ? t pcyc ssl hold time master t lag 18t spcyc slave 4 ? t pcyc data output delay time master 2.7 v vcc 5.5 v t od ?1 4n s 1.8 v vcc < 2.7 v ? 20 1.62 v vcc < 1.8 v ? 25 slave 2.7 v vcc 5.5 v ? 3 t pcyc + 65 1.8 v vcc < 2.7 v ? 3 tpcyc +85 1.62 v vcc < 1.8 v ? 3 tpcyc +95 data output hold time master t oh 0?n s slave 0 ? successive transmission delay time master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 4 t pcyc ? mosi and miso rise/ fall time output 2.7 v vcc 5.5 v t dr, t df ?1 0n s 1.8 v vcc < 2.7 v ? 15 1.62 v vcc < 1.8 v ? 20 input ? 1 s ssl rise/fall time output 2.7 v vcc 5.5 v t sslr, t sslf ?1 0n s 1.8 v vcc < 2.7 v ? 15 1.62 v vcc < 1.8 v ? 20 input ? 1 s slave access time 2.7 v vcc 5.5 v t sa ?6t pcyc c = 30pf figure 5.96 and figure 5.97 1.8 v vcc < 2.7 v ? 7 1.62 v vcc < 1.8 v ? 7 slave output release time 2.7 v vcc 5.5 v t rel ?5t pcyc 1.8 v vcc < 2.7 v ? 6 1.62 v vcc < 1.8 v ? 6
r01ds0041ej0150 rev.1.50 page 173 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note 1. t pcyc : pclk cycle table 5.58 timing of on-chi p peripheral modules (4) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c when high-drive output is selected by the drive capacity register item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master) t spcyc 4 65536 t pcyc c = 30 pf figure 5.91 sck clock cycle input (slave) 6 65536 sck input clock high pulse width t spckwh 0.4 0.6 t spcyc sck input clock low pulse width t spckwl 0.4 0.6 t spcyc sck output clock high pulse width 2.7 v vcc 5.5 v t spckwh 0.4 0.6 t spcyc 1.8 v vcc < 2.7 v 0.35 0.65 1.62 v vcc < 1.8 v 0.35 0.65 sck output clock low pulse width 2.7 v vcc 5.5 v t spckwl 0.4 0.6 t spcyc 1.8 v vcc < 2.7 v 0.35 0.65 1.62 v vcc < 1.8 v 0.35 0.65 sck clock rise/fall time t spckr, t spckf ?20ns data input setup time (master) 2.7 v vcc 5.5 v t su 65 ? ns c = 30 pf figure 5.92 to figure 5.97 1.8 v vcc < 2.7 v 75 ? 1.62 v vcc < 1.8 v 80 ? data input setup time (slave) 40 ? data input hold time t h 40 ? ns ss input setup time t lead 6?t pcyc ss input hold time t lag 6?t pcyc data output delay time (master) t od ?40ns data output delay time (slave) 2.7 v vcc 5.5 v ? 65 1.8 v vcc < 2.7 v ? 85 1.62 v vcc < 1.8 v ? 95 data output hold time t oh ?10 ? ns data rise/fall time t dr, t df ?20ns ss input rise/fall time t sslr, t sslf ?20ns slave access time t sa ?6t pcyc c = 30 pf figure 5.96 and figure 5.97 slave output release time t rel ?6t pcyc
r01ds0041ej0150 rev.1.50 page 174 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note: ? t iiccyc : riic internal reference count clock (iic ) cycle note 1. the value in parentheses is used when the icmr3.nf[1:0] bits are set to 11b while a digital filter is enabled with the i cfer.nfe bits = 1. note 2. c b indicates the total capacity of the bus line. table 5.59 timing of on-chi p peripheral modules (5) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, fpclkb = up to 32 mhz, t a = ?40 to +105c item symbol min.* 1, * 2 max. unit test conditions riic (standard mode, smbus) scl input cycle time t scl 6 (12) t iiccyc + 1300 ? ns figure 5.98 scl input high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl input low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda input rise time t sr ? 1000 ns scl, sda input fall time t sf ? 300 ns scl, sda input spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda input bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 1000 ? ns stop condition input setup time t stos 1000 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf riic (fast mode) scl input cycle time t scl 6 (12) t iiccyc + 600 ? ns figure 5.98 scl input high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl input low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda input rise time t sr 20 + 0.1c b 300 ns scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda input bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 300 ? ns stop condition input setup time t stos 300 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf
r01ds0041ej0150 rev.1.50 page 175 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note: ? t pcyc : pclk cycle note 1. c b indicates the total capacity of the bus line. note 2. this applies when the smr.cks[1:0] bits = 00b and the sn fr.nfcs[2:0] bits = 010b while the snfr.nfe bit = 1 and the digi tal filter is enabled. table 5.60 timing of on-chi p peripheral modules (6) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, fpclkb = up to 32 mhz, t a = ?40 to +105c when high-drive output is selected by the drive capacity register item symbol min.* 1 max. unit test conditions simple iic (standard mode) sda input rise time t sr ? 1000 ns figure 5.98 sda input fall time t sf ? 300 ns sda input spike pulse removal time t sp 04 t pcyc * 2 ns data input setup time t sdas 250 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf simple iic (fast mode) scl, sda input rise time t sr 20 + 0.1c b 300 ns figure 5.98 scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 04 t pcyc * 2 ns data input setup time t sdas 100 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf
r01ds0041ej0150 rev.1.50 page 176 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.83 i/o port input timing figure 5.84 mtu/tpu input/output timing figure 5.85 mtu/tpu clock input timing figure 5.86 poe# input timing port pclk t prw output compare output input capture input pclk t ticw mtclka to mtclkd pclk t tckwl t tckwh poen# input pclk t poew
r01ds0041ej0150 rev.1.50 page 177 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.87 8-bit timer clock input timing figure 5.88 sck clock input timing figure 5.89 sci input/output timing: clock synchronous mode figure 5.90 a/d converter external trigger input timing pclk tmci0 to tmci3 t tmcwl t tmcwh t sckw t sckr t sckf t scyc sckn (n = 0 to 12) t txd t rxs t rxh txdn rxdn sckn n = 0 to 12 adtrg0# pclk t trgw
r01ds0041ej0150 rev.1.50 page 178 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.91 rspi clock timing and simple spi clock timing sckn master select output sckn slave select input (n = 0 to 12) t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 vcc, v ol = 0.3 vcc, v ih = 0.7 vcc, v il = 0.3 vcc rspcka master select output rspcka slave select input simple spi rspi
r01ds0041ej0150 rev.1.50 page 179 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.92 rspi timing (master, cpha = 0) (b it rate: pclkb set to division ratio other than divided by 2) and simple sp i timing (master, ckph = 1) figure 5.93 rspi timing (master, cpha = 0) (bit rate: pclkb set to divided by 2) t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out sckn ckpol = 0 output sckn ckpol = 1 output smison input smosin output (n = 0 to 12) simple spi rspi ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output lsb in t dr, t df t su t hf t lead t td t lag t sslr, t sslf t oh t od msb in msb out data lsb out idle msb out msb in data t hf
r01ds0041ej0150 rev.1.50 page 180 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.94 rspi timing (master, cpha = 1) (b it rate: pclkb set to division ratio other than divided by 2) and simple sp i timing (master, ckph = 0) figure 5.95 rspi timing (master, cpha = 1) (bit rate: pclkb set to divided by 2) t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od sckn ckpol = 0 output sckn ckpol = 1 output smison input smosin output (n = 0 to 12) simple spi rspi ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output t dr, t df t hf t lead t td t lag t sslr, t sslf t oh data msb in msb out data lsb out idle msb out t od ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output msb in lsb in t su t h
r01ds0041ej0150 rev.1.50 page 181 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.96 rspi timing (slave, cpha = 0) and simple spi timing (slave, ckph = 1) figure 5.97 rspi timing (slave, cpha = 1) and simple spi timing (slave, ckph = 0) t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel sckn ckpol = 0 input sckn ckpol = 1 input smison output smosin input (n = 0 to 12) simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out sckn ckpol = 1 input sckn ckpol = 0 input smison output smosin input (n = 0 to 12) simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input
r01ds0041ej0150 rev.1.50 page 182 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.98 riic bus interface input/output timing and simple iic bus interface input/output timing test conditions v ih = vcc 0.7, v il = vcc 0.3 sda scl v ih v il t stah t sclh t scll p *1 s *1 t sf t sr t scl t sdah t sdas t stas t sp t stos p *1 t buf sr *1 note 1. s, p, and sr indicate the following conditions, respectively. s : start condition p : stop condition sr : restart condition
r01ds0041ej0150 rev.1.50 page 183 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.4 a/d conversion characteristics note: ? pclkd must be set to 40 mhz or lower when hoco is to be selected as the a/d conversion clock. the characteristics apply when no pin functions other than a/d conver ter input are used. absolute accuracy in cludes quantization errors. offset error, full-scale error, dnl differential nonlinearity error, and inl integral nonlinearity error do not include quantization errors. note: ? when using the channel-dedicated sample-and-hold circuit, use the an000 to an002 analog input voltage (v an ) that satisfies all the following conditions: 0.25 v v an avcc0 - 0.25 v, v an vrefh0, and avcc0 2.7 v. note 1. the conversion time is the sum of the sampling time and t he comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the value in parentheses indicates the sampling time. note 3. when using the temperature sensor, use it when avcc0 = vrefh0. figure 5.99 avcc0 to vrefh0 voltage range table 5.61 a/d conversion characteristics (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh0 2.7 v, avcc0-0.9 v vrefh0 avcc0* 3 , vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions a/d conversion clock frequency (fpclkd) 1 ? 50 mhz resolution ? ? 12 bit conversion time* 1 (operation at fpclkd = 50 mhz) permissible signal source impedance (max.) = 0.5 k ? 1.0 (0.4)* 2 ? ? s sampling in 20 states permissible signal source impedance (max.) = 1 k ? 1.1 (0.5)* 2 ? ? sampling in 25 states permissible signal source impedance (max.) = 5 k ? 1.5 (0.9)* 2 ? ? sampling in 45 states analog input capacitance ? ? 30 pf offset error ? 0.5 4.5 lsb high-precision channel 7.5 normal-precision channel full-scale error ? 0.75 4.5 lsb high-precision channel 7.5 normal-precision channel quantization error ? 0.5 ? lsb absolute accuracy ? 1.25 5.0 lsb high-precision channel ? 1.25 8.0 lsb normal-precision channel dnl differential nonlinearity error ? 1.0 ? lsb inl integral nonlinearity error ? 1.0 3.0 lsb 1.0 2.0 3.0 4.0 5.0 avcc0 1.0 2.0 3.0 4.0 5.0 vrefh0 3.6 1.8 1.62 1.8 1.62 2.7 2.7 4.6 characteristics listed in table 5.64 characteristics listed in table 5.61 characteristics listed in table 5.65
r01ds0041ej0150 rev.1.50 page 184 of 221 oct 18, 2013 rx210 group 5. electrical characteristics table 5.62 channel classification for a/d converter classification channel channel-dedicated sample-and-hold circuit conditions high-precision channel an000 to an002 used avcc0 = 2.7 to 5.5 v avcc0 - 0.9 v vrefh0 avcc0 vrefh0 2.7 v avss0 = vrefl0 = 0 v 0.25 v v an avcc0 - 0.25 v v an vrefh0 it is disallowed to use pins an000 to an007 as digital outputs when the a/d converter is used. not used avcc0 = 1.62 to 5.5 v when avcc0 1.8 v, avcc0 - 0.9 v vrefh0 avcc0 vrefh0 1.8 v when avcc0 < 1.8 v, vrefh0 = avcc0 avss0 = vrefl0 = 0 v 0 v v an vrefh0 an003 to an007 ? normal-precision channel an008 to an015 ? table 5.63 a/d internal reference voltage characteristics conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, ta = ? 40 to +105c item min. typ. max. unit test conditions a/d internal reference voltage 1.35 1.50 1.65 v
r01ds0041ej0150 rev.1.50 page 185 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note: ? the characteristics apply when no pin functions other t han a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl differ ential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note: ? when using the channel-dedicated sample-and-hold circuit, use the an000 to an002 analog input voltage (v an ) that satisfies all the following conditions: 0.25 v v an avcc0 - 0.25 v, v an vrefh0, and avcc0 2.7 v. note 1. the conversion time is the sum of the sampling time and t he comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the value in parentheses indicates the sampling time. note 3. when using the temperature sensor, use it when avcc0 = vrefh0. note: ? the characteristics apply when no pin functions other t han a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl differ ential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time and t he comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the value in parentheses indicates the sampling time. table 5.64 a/d conversion characteristics (2) conditions: vcc = avcc0 = 1.8 to 3.6 v, 1.8 v vrefh0 2.7 v, avcc0-0.9 v vrefh0 avcc0* 3 , vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions a/d conversion clock frequency (fpclkd) 1 ? 25 mhz resolution ? ? 12 bit conversion time* 1 (operation at fpclkd = 25 mhz) permissible signal source impedance (max.) = 1 k ? 2.0 (0.8)* 2 ? ? s sampling in 20 states permissible signal source impedance (max.) = 5 k ? 2.2 (1.0)* 2 ? ? sampling in 25 states analog input capacitance ? ? 30 pf offset error ? 0.5 7.5 lsb full-scale error ? 1.25 7.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 3.0 8.0 lsb dnl differential nonlinearity error ? 1.25 ? lsb inl integral nonlinearity error ? 1.5 3.0 lsb table 5.65 a/d conversion characteristics (3) conditions: vcc = avcc0 = 1.62 to 1.8 v, vrefh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions a/d conversion clock frequency (fpclkd) 1 ? 12.5 mhz resolution ? ? 12 bit conversion time* 1 (operation at fpclkd = 12.5 mhz) permissible signal source impedance (max.) = 1 k ? 3.36 (0.96)* 2 ? ? s sampling in 12 states permissible signal source impedance (max.) = 5 k ? 3.6 (1.2)* 2 ? ? sampling in 15 states analog input capacitance ? ? 30 pf offset error ? 0.5 7.5 lsb full-scale error ? 1.25 7.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 2.75 8.0 lsb dnl differential nonlinearity error ? 1.25 ? lsb inl integral nonlinearity error ? 1.25 3.0 lsb
r01ds0041ej0150 rev.1.50 page 186 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.100 internal equivalent circuit of analog input pin table 5.66 sampling time conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. unit test conditions sampling time high-precision channel ts 0.2 + 0.14 r0 (k ? ) s figure 5.100 normal-precision channel 0.35 + 0.14 r0 (k ? ) r0 ani rx210
r01ds0041ej0150 rev.1.50 page 187 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.101 illustration of a/d converter characteristic terms absolute accuracy absolute accuracy is the difference between output code based on the theoretical a/d conversion characteristics, and the actual a/d conversion result. when measur ing absolute accuracy, the voltage at th e midpoint of the width of analog input voltage (1-lsb width), that can m eet the expectation of outp utting an equal code based on the theoretical a/d conversion characteristics, is us ed as an analog input voltage. for example, if 12-bit resolution is used and if reference voltage (vrefh0 = 5.12 v), then 1-lsb width becomes 1.25 mv, and 0 mv, 1.25 mv, 2.5 mv , ... are used as analog input voltages. if analog input voltage is 10 mv, absolu te accuracy = 5 lsb means that the actua l a/d conversion result is in the range of 003h to 00dh though an output code, 008h, can be expect ed from the theoretical a/d conversion characteristics. integral nonlinearity error (inl) integral nonlinearity error is the maximum deviation between the ideal line when the meas ured offset and full-scale errors are zeroed, and the actual output code. integral nonlinearity error (inl) actual a/d conversion characteristic ideal a/d conversion characteristic analog input voltage offset error absolute accuracy differential nonlinearity error (dnl) full-scale error fffh 000h 0 ideal line of actual a/d conversion characteristic 1-lsb width for ideal a/d conversion characteristic differential nonlinearity error (dnl) 1-lsb width for ideal a/d conversion characteristic vrefh0 (full-scale) a/d converter output code
r01ds0041ej0150 rev.1.50 page 188 of 221 oct 18, 2013 rx210 group 5. electrical characteristics differential nonlinearity error (dnl) differential nonlinearity error is the difference between 1-lsb width base d on the ideal a/d conver sion characteristics and the width of the actually output code. offset error offset error is the difference between a transition point of the ideal first output code and the actual first output code. full-scale error full-scale error is the differen ce between a transition point of the ideal last output code and the actual last output code.
r01ds0041ej0150 rev.1.50 page 189 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.5 d/a conversion characteristics 5.6 temperature sensor characteristics table 5.67 d/a conversion characteristics (1) conditions: vcc = avcc0 = 2.7 to 5. 5 v, vrefh = 2.7 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, fpclkb = up to 32 mhz, t a = ?40 to +105c item min. typ. max. unit test conditions resolution ? ? 10 bit conversion time ? ? 3.0 s 20-pf capacitive load absolute accuracy ? 3.0 5.0 lsb 4-m ? resistive load ?? 4 . 0l s b8 - m ? resistive load ro output resistance ? 4.1 ? k ? table 5.68 d/a conversion characteristics (2) conditions: vcc = avcc0 = 2.7 to 5. 5 v, vrefh =1.8 v to avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, fpclkb = up to 32 mhz, t a = ?40 to +105c item min. typ. max. unit test conditions resolution ? ? 10 bit conversion time ? ? 10.0 s 20-pf capacitive load absolute accuracy ? 5.0 6.0 lsb 4-m ? resistive load ?? 5 . 0l s b8 - m ? resistive load ro output resistance ? 4.1 ? k ? table 5.69 temperature sensor characteristics conditions: vcc = avcc0 = vrefh0 = 1.8 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions relative accuracy DD 1.0 D c temperature slope 1.8 avcc0 < 2.7 DD 7.27 D mv/c pgagain = 00b 2.7 avcc0 < 3.6 D 10.46 D pgagain = 01b 3.6 avcc0 < 4.5 D 13.98 D pgagain = 10b 4.5 avcc0 5.5 D 21.65 D pgagain = 11b output voltage (@ 25c) DD 1.375 D v vcc = 3.6 v temperature sensor start time t start DD 80 s figure 5.102 sampling time D 30 72 300 s pga restart time t rst_pga DD 40 s
r01ds0041ej0150 rev.1.50 page 190 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.102 a/d conversion timing example of the temperature sensor (two conversions performed) 5.7 comparator characteristics note 1. when the digital filter is disabled. table 5.70 comparator characteristics conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions comparator a external reference voltage input range lvref 1.4 D vcc v external comparison voltage (cmpa1, cmpa2) input range vi ?0.3 D vcc + 0.3 v offset DD 50 150 mv comparator output delay time* 1 DD 3 D s at falling edge vi = lvref ? 110 mv D 2 D s at falling edge vi < lvref ? 1 v D 3 D s at rising edge vi = lvref + 160 mv D 1.5 D s at rising edge vi > lvref + 1 v comparator operating current icmpa D 0.5 D a vcc = 5.0 v comparator b input reference voltage for cvrefb0, cvrefb1 vref 0 D vcc ? 1.4 v input voltage for cmpb0, cmpb1 vi ?0.3 D vcc + 0.3 v offset DD 10 100 mv comparator output delay time t d DD 1s vi = vref + 100 mv comparator operating current icmpb D 75 150 a vcc = 5.0 v for total two channels a/d interrupt request (s12adi0) tsen pgaen t start t rst_pga trigger to start a/d conversion from the temperature sensor (internal signal) a/d converter a/d activation trigger pga is stopped idle a/d conversion sampling idle a/d conversion sampling idle 1st result of a/d conversion of the temperature sensor output 2nd result of a/d conversion of the temperature sensor output temperature sensor is stopped temperature sensor is operating pga is operating pga is operating pga is stopped automatic clearing automatic clearing a/d activation trigger adtsdr register
r01ds0041ej0150 rev.1.50 page 191 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.8 power-on reset circuit and voltage detecti on circuit characteristics note: ? these characteristics apply when noise is not superimposed on the power supply. note 1. when the cpu is in a mode other than software standby and deep software standby modes, when the cpu transits to software standby mode with the fhssbycr.softcut[2] bi t set to 0, or when the cpu transits to deep software standby mode with the dpsbycr.deepcut1 bit set to 0. note 2. when the cpu transits to software standby mode with th e fhssbycr.softcut[2] bit set to 1 or when the cpu transits to deep software standby mode with the dpsbycr.deepcut1 bit set to 1. note 3. # in the symbol vdet0_# denotes the value of the ldsel[1:0] bits. note 4. # in the symbol vdet1_# denotes the value of the lvdlvlr.lvd1lvl[3:0] bits. table 5.71 power-on reset circuit and voltage detection circuit characteristics (1) conditions: vcc = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) low power consumption function disabled* 1 v por 1.30 1.40 1.55 v figure 5.103 and figure 5.104 low power consumption function enabled* 2 1.00 1.20 1.45 voltage detection circuit (lvd0)* 3 v det0_0 3.65 3.80 3.95 v figure 5.105 v det0_1 2.70 2.80 2.90 v det0_2 1.80 1.90 2.00 v det0_3 1.62 1.72 1.82 voltage detection circuit (lvd1)* 4 v det1_0 4.00 4.15 4.30 v figure 5.106 at falling edge vcc v det1_1 3.85 4.00 4.15 v det1_2 3.70 3.85 4.00 v det1_3 3.55 3.70 3.85 v det1_4 3.40 3.55 3.70 v det1_5 3.25 3.40 3.55 v det1_6 3.10 3.25 3.40 v det1_7 2.95 3.10 3.25 v det1_8 2.85 2.95 3.05 v det1_9 2.70 2.80 2.90 v det1_a 2.55 2.65 2.75 v det1_b 2.40 2.50 2.60 v det1_c 2.25 2.35 2.45 v det1_d 2.10 2.20 2.30 v det1_e 1.95 2.05 2.15 v det1_f 1.80 1.90 2.00
r01ds0041ej0150 rev.1.50 page 192 of 221 oct 18, 2013 rx210 group 5. electrical characteristics note: ? these characteristics apply when noise is not superimposed on the power supply. note 1. # in the symbol vdet2_# denotes the value of the lvdlvlr.lvd2lvl[3:0] bits. note 2. the minimum vcc down time indicates the time when v cc is below the minimum value of voltage detection levels v por , v det0 , v det1, and v det2 for the por/lvd. table 5.72 power-on reset circuit and voltage detection circuit characteristics (2) conditions: vcc = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions voltage detection level voltage detection circuit (lvd2)* 1 v det2_0 4.00 4.15 4.30 v figure 5.107 at falling edge vcc v det2_1 3.85 4.00 4.15 v det2_2 3.70 3.85 4.00 v det2_3 3.55 3.70 3.85 v det2_4 3.40 3.55 3.70 v det2_5 3.25 3.40 3.55 v det2_6 3.10 3.25 3.40 v det2_7 2.95 3.10 3.25 v det2_8 2.85 2.95 3.05 v det2_9 2.70 2.80 2.90 v det2_a 2.55 2.65 2.75 v det2_b 2.40 2.50 2.60 v det2_c 2.25 2.35 2.45 v det2_d 2.10 2.20 2.30 v det2_e 1.95 2.05 2.15 v det2_f 1.80 1.90 2.00 v cmpa2 1.18 1.33 1.48 exvccinp2 = 1 internal reset time power-on reset time t por ? 9 ? ms figure 5.104 voltage monitoring 0 reset time t lvd0 ? 9 ? figure 5.105 voltage monitoring 1 reset time t lvd1 ? 1.4 ? figure 5.106 voltage monitoring 2 reset time t lvd2 ? 1.4 ? figure 5.107 minimum vcc down time* 2 t voff 200 ? ? s figure 5.103 response delay time t det ? ? 200 s figure 5.104 lvd operation stabilization time (after lvd is enabled) td (e-a) ? ? 15 s figure 5.106 and figure 5.107 power-on reset enable time t w(por) 1 ? ? ms figure 5.104 vcc = 0.9 v or lower hysteresis width (lvd1 and lvd2) v lvh ? 100 ? mv when selection is from among vdetx_0 to 7. ? 50 ? when selection is from among vdetx_8 to f.
r01ds0041ej0150 rev.1.50 page 193 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.103 voltage detection reset timing figure 5.104 power-on reset timing figure 5.105 voltage detection circuit timing (v det0 ) t voff t por t det t det v por vcc internal reset signal (active-low) v por 0.9 v t w(por) t por t det vcc *1 internal reset signal (active-low) note 1. t w(por) is the time required for a power-on reset to be enabled while the external power vcc is being held below the valid voltage (0.9 v). when vcc turns on, maintain t w(por) for 1 ms or more. v por t voff t lvd0 t det v det0 vcc internal reset signal (active-low) t det
r01ds0041ej0150 rev.1.50 page 194 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.106 voltage detection circuit timing (v det1 ) figure 5.107 voltage detection circuit timing (v det2 ) t voff v det1 vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (active-low) when lvd1rn = l when lvd1rn = h v lvh t lvd1 t voff v det2 vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (active-low) when lvd2rn = l when lvd2rn = h v lvh t lvd2
r01ds0041ej0150 rev.1.50 page 195 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.9 oscillation stop detection timing figure 5.108 oscillation stop detection timing table 5.73 oscillation stop detection circuit characteristics conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions detection time t dr ? ? 1 ms figure 5.108 t dr main clock or pll clock ostdsr.ostdf loco clock iclk
r01ds0041ej0150 rev.1.50 page 196 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.10 rom (flash memory for code storage) characteristics [chip version a] note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogr am/ erase cycle is n times (n = 1000), erasing can be performed n ti mes for each block. for instance, when 128-byte programming is performed 16 times for different addresses in 2-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for se veral times as one erasing is not enabled (overwriting is prohibited). note 2. this result is obtained from reliability testing. [chip versions b and c] note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogr am/ erase cycle is n times (n = 1000), erasing can be performed n ti mes for each block. for instance, when 128-byte programming is performed 16 times for different addresses in 2-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for se veral times as one erasing is not enabled (overwriting is prohibited). note 2. this result is obtained from reliability testing. table 5.74 rom (flash memory for code storage) characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n pec 1000 ? ? times data hold time t drp 10* 2 ? ? year table 5.75 rom (flash memory for code storage) characteristics (2) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n pec 10000 ? ? times data hold time after 1000 times of n pec t drp 30* 2 ? ? year ta = +85c after 10000 times of n pec 1* 2 ? ? year
r01ds0041ej0150 rev.1.50 page 197 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip versions a and c] table 5.76 rom (flash memory for code storage) characteristics (3) : high-speed operating mode, middle-speed operating mode 1a conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time when n pec 100 times 2 bytes t p2 ? 0.52 4.8 ? 0.19 2.5 ms 8 bytes t p8 ? 0.52 4.9 ? 0.19 2.5 128 bytes t p128 ? 1.50 10.7 ? 0.57 4.8 programming time when n pec > 100 times 2 bytes t p2 ? 0.61 5.7 ? 0.23 3.0 ms 8 bytes t p8 ? 0.61 6.2 ? 0.23 3.2 128 bytes t p128 ? 1.71 13.2 ? 0.65 6.0 erasure time when n pec 100 times 2 kbytes t e2k ? 17.0 92.9 ? 11.0 29 ms erasure time when n pec > 100 times 2 kbytes t e2k ? 20.8 195.8 ? 13.5 60 ms suspend delay time during programming (in programming/erasure priority mode) t spd ??0 . 9??0 . 8m s first suspend delay time during programming (in suspend priority mode) t spsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t spsd2 ??0 . 9??0 . 8m s suspend delay time during erasing (in programming/erasure priority mode) t sed ??0 . 9??0 . 8m s first suspend delay time during erasing (in suspend priority mode) t sesd1 ? ? 220 ? ? 120 s second suspend delay ti me during erasing (in suspend priority mode) t sesd2 ??0 . 9??0 . 8m s fcu reset time t fcur 20 s or longer and fclk 6 or greater ? ? 20 s or longer and fclk 6 or greater ?? s
r01ds0041ej0150 rev.1.50 page 198 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip versions a and c] note 1. the operating frequency is 20 mhz (max.) when the vo ltage is in the range from 1.62 v to less than 1.8 v. table 5.77 rom (flash memory for code storage) characteristics (4) : middle-speed operating mode 1b conditions: vcc = avcc0 = 1.62 to 3.6 v, vrefh = vr efh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz* 1 unit min. typ. max. min. typ. max. programming time when n pec 100 times 2 bytes t p2 ? 0.69 6.0 ? 0.30 3.5 ms 8 bytes t p8 ? 0.69 6.0 ? 0.30 3.5 128 bytes t p128 ? 1.76 14.2 ? 0.85 8.3 programming time when n pec > 100 times 2 bytes t p2 ? 0.81 7.1 ? 0.35 4.2 ms 8 bytes t p8 ? 0.81 7.6 ? 0.35 4.5 128 bytes t p128 ? 1.99 17.5 ? 0.96 10 erasure time when n pec 100 times 2 kbytes t e2k ? 24.5 113.7 ? 19.0 46 ms erasure time when n pec > 100 times 2 kbytes t e2k ? 29.8 225.8 ? 23.2 90 (1000 times n pec > 100 times), 98 (10000 times n pec > 1000 times) ms suspend delay time during programming (in programming/erasure priority mode) t spd ??1.7?? 1.6 ms first suspend delay time during programming (in suspend priority mode) t spsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t spsd2 ??1.7?? 1.6 ms suspend delay time during erasing (in programming/erasure priority mode) t sed ??1.7?? 1.6 ms first suspend delay time during erasing (in suspend priority mode) t sesd1 ? ? 220 ? ? 120 s second suspend delay time during erasing (in suspend priority mode) t sesd2 ??1.7?? 1.6 ms fcu reset time t fcur 20 s or longer and fclk 6 or greater ? ? 20 s or longer and fclk 6 or greater ?? s
r01ds0041ej0150 rev.1.50 page 199 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b] table 5.78 rom (flash memory for code storage) characteristics (5) : middle-speed operating modes 1a and 2a conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time when n pec 100 times 2 bytes t p2 ? 0.19 4.3 ? 0.12 2.0 ms 8 bytes t p8 ? 0.19 4.4 ? 0.12 2.0 128 bytes t p128 ? 0.67 10.7 ? 0.41 4.8 programming time when n pec > 100 times 2 bytes t p2 ? 0.23 5.3 ? 0.15 2.5 ms 8 bytes t p8 ? 0.23 5.4 ? 0.15 2.5 128 bytes t p128 ? 0.80 13.2 ? 0.48 6.0 erasure time when n pec 100 times 2 kbytes t e2k ? 13.0 92.9 ? 10.5 29 ms erasure time when n pec > 100 times 2 kbytes t e2k ? 15.9 176.9 ? 12.8 60 ms suspend delay time during programming (in programming/erasure priority mode) t spd ??0 . 9??0 . 8m s first suspend delay time during programming (in suspend priority mode) t spsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t spsd2 ??0 . 9??0 . 8m s suspend delay time during erasing (in programming/erasure priority mode) t sed ??0 . 9??0 . 8m s first suspend delay time during erasing (in suspend priority mode) t sesd1 ? ? 220 ? ? 120 s second suspend delay ti me during erasing (in suspend priority mode) t sesd2 ??0 . 9??0 . 8m s fcu reset time t fcur 20 s or longer and fclk 6 or greater ? ? 20 s or longer and fclk 6 or greater ?? s
r01ds0041ej0150 rev.1.50 page 200 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b] note 1. the operating frequency is 20 mhz (max.) when the vo ltage is in the range from 1.62 v to less than 1.8 v. table 5.79 rom (flash memory for code storage) characteristics (6) : middle-speed operating modes 1b and 2b conditions: vcc = avcc0 = 1.62 to 3.6 v, vrefh = vr efh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz* 1 unit min. typ. max. min. typ. max. programming time when n pec 100 times 2 bytes t p2 ? 0.25 5.0 ? 0.21 2.8 ms 8 bytes t p8 ? 0.25 5.3 ? 0.21 3.0 128 bytes t p128 ? 0.92 14.0 ? 0.65 8.3 programming time when n pec > 100 times 2 bytes t p2 ? 0.31 6.2 ? 0.26 3.5 ms 8 bytes t p8 ? 0.31 6.6 ? 0.26 3.7 128 bytes t p128 ? 1.09 17.5 ? 0.77 10.0 erasure time when n pec 100 times 2 kbytes t e2k ? 21.0 113.7 ? 18.5 46 ms erasure time when n pec > 100 times 2 kbytes t e2k ? 25.6 220.6 ? 22.5 90 (1000 times n pec > 100 times), 98 (10000 times n pec > 1000 times) ms suspend delay time during programming (in programming/erasure priority mode) t spd ??1.7?? 1.6 ms first suspend delay time during programming (in suspend priority mode) t spsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t spsd2 ??1.7?? 1.6 ms suspend delay time during erasing (in programming/erasure priority mode) t sed ??1.7?? 1.6 ms first suspend delay time during erasing (in suspend priority mode) t sesd1 ? ? 220 ? ? 120 s second suspend delay time during erasing (in suspend priority mode) t sesd2 ??1.7?? 1.6 ms fcu reset time t fcur 20 s or longer and fclk 6 or greater ? ? 20 s or longer and fclk 6 or greater ?? s
r01ds0041ej0150 rev.1.50 page 201 of 221 oct 18, 2013 rx210 group 5. electrical characteristics 5.11 e2 dataflash characteristics [chip version a] note 1. the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 100000 ), erasing can be performed n times for each block. for instance, when 8-byte programming is performed 16 times for different addresses in 128-byte block and then the entire block is eras ed, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (ove rwriting is prohibited). note 2. this result is obtained from reliability testing. [chip versions b and c] note 1. the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 100000 ), erasing can be performed n times for each block. for instance, when 8-byte programming is performed 16 times for different addresses in 128-byte block and then the entire block is eras ed, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (ove rwriting is prohibited). note 2. this result is obtained from reliability testing. table 5.80 e2 dataflash characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n dpec 100000 ? ? times data hold time t drp 10* 2 ? ? year table 5.81 e2 dataflash characteristics (2) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n dpec 100000 ? ? times data hold time after 100000 times of n dpec t drp 30* 2 ? ? year ta = +85c
r01ds0041ej0150 rev.1.50 page 202 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip versions a and c] table 5.82 e2 dataflash characteristics (3) : high-speed operating mode, middle-speed operating mode 1a conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time when n dpec 100 times 2 bytes t dp2 ? 0.40 4.4 ? 0.16 2.0 ms 8 bytes t dp8 ? 0.45 5.1 ? 0.17 2.2 programming time when n dpec > 100 times 2 bytes t dp2 ? 0.62 6.4 ? 0.25 3.0 ms 8 bytes t dp8 ? 0.69 7.5 ? 0.26 3.2 erasure time when n dpec 100 times 128 bytes t de128 ? 5.6 27.1 ? 2.8 8 ms erasure time when n dpec > 100 times 128 bytes t de128 ? 6.8 45.1 ? 3.4 12 ms blank check time 2 bytes t dbc2 ??98??35 s 2 kbytes t dbc2k ??16??2.5ms suspend delay time during programming (in programming/erasure priority mode) t dspd ??0.9??0.8ms first suspend delay time during programming (in suspend priority mode) t dspsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t dspsd2 ??0.9??0.8ms suspend delay time during erasing (in programming/erasure priority mode) t dsed ??0.9??0.8ms first suspend delay time during erasing (in suspend priority mode) t dsesd1 ? ? 220 ? ? 120 s second suspend delay ti me during erasing (in suspend priority mode) t dsesd2 ??0.9??0.8ms
r01ds0041ej0150 rev.1.50 page 203 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip versions a and c] note 1. the operating frequency is 20 mhz (max.) when the vo ltage is in the range from 1.62 v to less than 1.8 v. table 5.83 e2 dataflash characteristics (4) : middle-speed operating mode 1b conditions: vcc = avcc0 = 1.62 to 3.6 v, vrefh = vr efh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz* 1 unit min. typ. max. min. typ. max. programming time when n dpec 100 times 2 bytes t dp2 ? 0.52 5.1 ? 0.24 2.8 ms 8 bytes t dp8 ? 0.57 6.0 ? 0.26 3.2 programming time when n dpec > 100 times 2 bytes t dp2 ? 0.77 7.6 ? 0.36 4.2 ms 8 bytes t dp8 ? 0.84 8.8 ? 0.38 4.5 erasure time when n dpec 100 times 128 bytes t de128 ? 6.8 32.5 ? 4.4 12 ms erasure time when n dpec > 100 times 128 bytes t de128 ? 8.2 51.4 ? 5.3 17 ms blank check time 2 bytes t dbc2 ??110??40 s 2 kbytes t dbc2k ??16.3??2.6ms suspend delay time during programming (in programming/erasure priority mode) t dspd ??1.7??1.6ms first suspend delay time during programming (in suspend priority mode) t dspsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t dspsd2 ??1.7??1.6ms suspend delay time during erasing (in programming/erasure priority mode) t dsed ??1.7??1.6ms first suspend delay time during erasing (in suspend priority mode) t dsesd1 ? ? 220 ? ? 120 s second suspend delay ti me during erasing (in suspend priority mode) t dsesd2 ??1.7??1.6ms
r01ds0041ej0150 rev.1.50 page 204 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b] table 5.84 e2 dataflash characteristics (5) : high-speed operating mode, middle-speed operating modes 1a and 2a conditions: vcc = avcc0 = 2.7 to 5.5 v, vrefh = vrefh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time when n dpec 100 times 2 bytes t dp2 ? 0.19 4.4 ? 0.13 2.0 ms 8 bytes t dp8 ? 0.24 5.1 ? 0.13 2.2 programming time when n dpec > 100 times 2 bytes t dp2 ? 0.25 6.4 ? 0.17 3.0 ms 8 bytes t dp8 ? 0.32 7.5 ? 0.18 3.2 erasure time when n dpec 100 times 128 bytes t de128 ? 3.3 27.1 ? 2.5 8 ms erasure time when n dpec > 100 times 128 bytes t de128 ? 4.0 45.1 ? 3.0 12 ms blank check time 2 bytes t dbc2 ??98??35 s 2 kbytes t dbc2k ??16??2.5ms suspend delay time during programming (in programming/erasure priority mode) t dspd ??0.9??0.8ms first suspend delay time during programming (in suspend priority mode) t dspsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t dspsd2 ??0.9??0.8ms suspend delay time during erasing (in programming/erasure priority mode) t dsed ??0.9??0.8ms first suspend delay time during erasing (in suspend priority mode) t dsesd1 ? ? 220 ? ? 120 s second suspend delay ti me during erasing (in suspend priority mode) t dsesd2 ??0.9??0.8ms
r01ds0041ej0150 rev.1.50 page 205 of 221 oct 18, 2013 rx210 group 5. electrical characteristics [chip version b] note 1. the operating frequency is 20 mhz (max.) when the vo ltage is in the range from 1.62 v to less than 1.8 v. table 5.85 e2 dataflash characteristics (6) : middle-speed operating modes 1b and 2b conditions: vcc = avcc0 = 1.62 to 3.6 v, vrefh = vr efh0 = avcc0, vss = avss0 = vrefl = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz* 1 unit min. typ. max. min. typ. max. programming time when n dpec 100 times 2 bytes t dp2 ? 0.28 5.1 ? 0.20 2.8 ms 8 bytes t dp8 ? 0.32 6.0 ? 0.22 3.2 programming time when n dpec > 100 times 2 bytes t dp2 ? 0.36 7.6 ? 0.25 4.2 ms 8 bytes t dp8 ? 0.40 8.8 ? 0.28 4.5 erasure time when n dpec 100 times 128 bytes t de128 ? 4.8 32.4 ? 4.1 12 ms erasure time when n dpec > 100 times 128 bytes t de128 ? 5.8 51.4 ? 4.9 17 ms blank check time 2 bytes t dbc2 ??110??40 s 2 kbytes t dbc2k ??16.3??2.6ms suspend delay time during programming (in programming/erasure priority mode) t dspd ??1.7??1.6ms first suspend delay time during programming (in suspend priority mode) t dspsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t dspsd2 ??1.7??1.6ms suspend delay time during erasing (in programming/erasure priority mode) t dsed ??1.7??1.6ms first suspend delay time during erasing (in suspend priority mode) t dsesd1 ? ? 220 ? ? 120 s second suspend delay ti me during erasing (in suspend priority mode) t dsesd2 ??1.7??1.6ms
r01ds0041ej0150 rev.1.50 page 206 of 221 oct 18, 2013 rx210 group 5. electrical characteristics figure 5.109 flash memory program/erase suspend timing ? suspension during erasure fcu command fstatr0.frdy programming pulse ? suspension during programming program suspend ready not ready ready t spd programming fcu command fstatr0.frdy programming pulse ? suspension during programming ready not ready not ready t spsd1 fcu command fstatr0.frdy erasure pulse ? suspension during erasure erase suspend ready not ready ready t sed erasing in suspend priority mode in programming/erasure priority mode program suspend resume suspend resume suspend resume t spsd2 not ready t spsd1 programming programming programming application of the pulse stops application of the pulse continues fcu command erasure pulse ready not ready not ready t sesd1 erase suspend resume suspend resume suspend resume t sesd2 not ready t sesd1 erasing erasing erasing application of the pulse stops application of the pulse continues fstatr0.frdy
r01ds0041ej0150 rev.1.50 page 207 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions appendix 1. package dimensions information on the latest version of the package dimensions or mountings has been displayed in ?packages? on renesas electronics corporation website. figure a 145-pin tflga (ptlg0145ka-a) 0.5 z e z d 0.5 0.29 0.25 0.21b b 1 y 0.08 e 0.5 x a 1.05 e7 . 0 d7 . 0 reference symbol dimension in millimeters min nom max 0.29 0.34 0.39 0.08 w 0.20 v 0.15 ptlg0145ka-a 145f0g p-tflga145-7x7-0.50 0.1g mass[typ.] renesas code jeita package code previous code 1312 11 10 9 n m l k j index mark (laser mark) x4 v ab a b s ab s s y s 87654321 b c d e f g h a s a w s w b z e z d a e e e d b 1 m b m
r01ds0041ej0150 rev.1.50 page 208 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions figure b 144-pin lqfp (plqp0144ka-a) terminal cross section b 1 c 1 b p c 1.0 0.125 0.20 1.25 1.25 0.08 0.20 0.145 0.09 0. 270. 220.17 max n ommin dimension in millimeters symbol reference 20. 120. 019.9 d 20. 120. 019.9 e 1.4 a 2 22. 222. 021.8 22. 222. 021.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lfqfp144-20x20-0.50 1.2g mass[typ.] 144p6q-a / fp-144l / fp-144lv plqp0144ka-a renesas code jeita package code previous code f 1 36 37 72 73 108 109 144 *1 *2 *3 x index mark h e e d h d b p z d z e detail f c a l a 1 a 2 l 1 2. 1. dimensions "*1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. e y s s
r01ds0041ej0150 rev.1.50 page 209 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions figure c 100-pin tflga (ptlg0100ja-a) p-tflga100-7x7-0.65 0.1g mass[typ.] 100f0g ptlg0100ja-a renesas code jeita package code previous code 0.15 v 0.20 w 0.08 0.485 0.435 0.385 max nom min dimension in millimeters symbol reference 7.0 d 7.0 e 1.05 a x 0.65 e 0.10 y b 1 b 0.31 0.35 0.39 0.575 z d z e 0.575 index mark b w s w a s a h g f e d c b 12345678 ys s a v 4 (laser mark) index mark j k 910 d e e e a z d z e b b b 1 ms ab ms ab
r01ds0041ej0150 rev.1.50 page 210 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions figure d 100-pin tflga (ptlg0100ka-a) e e a b c d e f g h j k 12345678910 b a s ys index mark index mark (laser mark) x4 v a ws b ws d e z d z e a sab m sab m b 1 b 0.15 1.05 0.08 0.08 reference symbol dimension in millimeters min nom max d e v z d b 1 b 5.5 5.5 0.5 0.5 a 0.5 e w x y z e 0.20 0.250.21 0.29 0.340.29 0.39 p-tflga100-5.5x5.5-0.50 0.1g mass[typ.] 100f0m ptlg0100ka-a renesas code jeita package code previous code
r01ds0041ej0150 rev.1.50 page 211 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions figure e 69-pin wlbga (swbg0069la-a) q-e \ y ? 6($7,1*3/$1( % $ * ) ' ( + - & $%6 -[0 6 % $ 6 jeita package > code renesas > code previous > code mass(typ.)[g] s-wfbga69-3.91x4.26-0.40 swbg0069la-a h 0.02 specification reference symbol min nom max d e ee a a1 a2 b v (a3) n 3.86 3.91 3.96 4.21 4.26 4.31 h h 0.70 0.15 0.19 0.23 0.36 0.40 0.44 h h 0.22 0.27 0.4 0.4 69 h 0.32 (bsc) (bsc) 0.05 ed tolerance of package lateral profile number of terminals terminal pitch in length terminal diameter wafer thickness stand-off height profile height package length package width zd ze 0.305 0.48 0.355 0.53 0.405 0.58 overhang dimension in length overhang dimension in width terminal pitch in width term x 0.05 positional tolerance of terminals y 0.08 coplanarity se h h (bsc) (bsc) sd center terminal position in d-direction e1 3.2 3.2 (bsc) (bsc) d1 edge ball center to center in d-direction center terminal position in e-direction edge ball center to center in d-direction note: 1. ball pitch dimension is specified with the center of balls. 2. datum a and b are axes defined by the ball grid array, not by the pkg outline. dimensions in millimeters @0h 1. '?h?h?hkh}f?'?p?4?ft)*(f0dfgf1 2. hh?hlh|h? a lg b f?f?h?h?hlh?hth?h?hkh?h?hzh?h|g"&ff1 ? 2013 renesas electronics corporation. all rights reserved.
r01ds0041ej0150 rev.1.50 page 212 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions figure f 64-pin tflga (ptlg0064ja-a) 0.15 v 0.20 w previous code jeita package code renesas code ptlg0064ja-a 64f0g mass[typ.] 0.07g p-tflga64-6x6-0.65 0.08 0.470.430.39 maxnommin dimension in millimeters symbol reference 6.0 d 6.0 e 1.05 a x 0.65 e 0.10 y b 1 b 0.31 0.35 0.39 b w s w a s a h g f e d c b 12345678 s ys ab index mark sab v x4 (laser mark) index mark d e a b 1 b e e
r01ds0041ej0150 rev.1.50 page 213 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions figure g 100-pin lqfp (plqp0100kb-a) terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension " *3" does not include trim offset. index mark x 12 5 26 50 51 75 76 100 f *1 *3 *2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lfqfp100-14x14-0.50 e y s s
r01ds0041ej0150 rev.1.50 page 214 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions figure h 80-pin lqfp (plqp0080kb-a) detail f c a l 1 l a 1 a 2 index mark *2 *1 *3 f 80 61 60 41 40 21 20 1 x z e z d e h e d h d e b p 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. previous code jeita package code renesas code plqp0080kb-a 80p6q-a mass[typ.] 0.5g p-lfqfp80-12x12-0.50 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.1450.09 0.250.200.15 maxnommin dimension in millimeters symbol reference 12.112.011.9 d 12.112.011.9 e 1.4 a 2 14.214.013.8 14.214.013.8 1.7 a 0.20.1 0 0.70.50.3 l x 10 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section c bp c 1 b 1 y s s
r01ds0041ej0150 rev.1.50 page 215 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions figure i 80-pin lqfp (plqp0080ja-a) l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.10 e 0.65 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15. 816 . 016 .2 15. 816 . 016 .2 a 2 1.4 e 13.91 4.01 4.1 d 13.91 4.01 4.1 reference symbol dimension in millimeters min n om max 0. 27 0. 32 0.37 0.09 0.145 0.20 0.13 0.825 0.825 0.30 0.125 1.0 p-lqfp80-14x14-0.65 0.6g mass[typ.] fp-80w / fp-80wv plqp0080ja-a renesas code jeita package code previous code include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. c 1 c b p b 1 terminal cross section a 2 c l a 1 a l 1 detail f z e z d h e h d d e *2 *1 *3 f 80 61 60 41 40 21 20 1 index mark e b p m s ys
r01ds0041ej0150 rev.1.50 page 216 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions figure j 64-pin lqfp (plqp0064kb-a) terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension " *3" does not include trim offset. index mark *3 17 32 64 49 11 6 33 48 f *1 *2 x b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lfqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.250.200.15 maxnommin dimension in millimeters symbol reference 10.110.0 9.9 d 10.110.0 9.9 e 1.4 a 2 12.212.011.8 12.212.011.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s
r01ds0041ej0150 rev.1.50 page 217 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions figure k 64-pin lqfp (plqp0064ga-a) terminal cross section b1 c1 bp c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. *3 11 6 17 32 33 48 49 64 f *1 *2 x index mark d h d e h e e b p z d z e detail f c a a 2 a 1 l l 1 previous code jeita package code renesas code plqp0064ga-a 64p6u-a/ ? mass[typ.] 0.7g p-lqfp64-14x14-0.80 1.0 0.125 0.35 1.0 1.0 0.20 0.20 0.145 0.09 0.420.370.32 maxnom min dimension in millimeters symbol reference 14.1 14.0 13.9 d 14.1 14.0 13.9 e 1.4 a 2 16.2 16.0 15.8 16.2 16.0 15.8 1.7 a 0.2 0.1 0 0.70.50.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s
r01ds0041ej0150 rev.1.50 page 218 of 221 oct 18, 2013 rx210 group appendix 1. package dimensions figure l 48-pin lqfp (plqp0048kb-a) terminal cross section b 1 c 1 bp c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. detail f l 1 c a l a 1 a 2 *3 f 48 37 36 25 24 13 12 1 *1 *2 x index mark z e z d b p e h e h d d e previous code jeita package code renesas code plqp0048kb-a 48p6q-a mass[typ.] 0.2g p-lfqfp48-7x7-0.50 1.0 0.125 0.20 0.75 0.75 0.08 0.20 0.145 0.09 0.270.220.17 maxnommin dimension in millimeters symbol reference 7.17.06.9 d 7.17.06.9 e 1.4 a 2 9.29.08.8 9.29.08.8 1.7 a 0.20.1 0 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s
r01ds0041ej0150 rev.1.50 page 219 of 221 oct 18, 2013 rx210 group revision history revision history rx210 group datasheet rev. date description page summary 0.50 apr.15, 2011 ? first edition, issued 0.90 aug.10, 2011 1. overview 4 table 1.1 outline of specifications: po wer supply voltage/ operating frequency, changed 17, 21, 24, 26 table 1.5 to table 1.8 list of pins and pin functions (pin name: lvcmp2 ? cmpa2), changed 2. cpu 51 table 2.14 instructions that are converted into multiple micro-operations (multiplier: 32 32 ? 64 bits), (memory source operand), added 4. i/o registers 63 table 5.1 list of i/o registers (addres s order), soscwtcr, locowtcr2, hocowtcr2, added 114 to 116 table 5.1 list of i/o registers (address order): interrupt source priority register, changed 5. electrical characteristics 85 to 137 newly added 1.20 nov 28, 2012 all information on chip versions a, b, and c, corresponding descriptions and notes, added 48-pin products added, plqp0080ja-a 14 ? 14 mm, 0.65-mm pitch, package deleted features 1 description changed 1. overview 2 1.1 outline of specific ations: description, changed 2 to 5 table 1.1 outline of specifications, changed note 1, added 6 table 1.2 comparison of functi ons for different packages, changed 7 table 1.3 list of products, changed 8 to 10 tables 1.4 to 1.7 list of products, added 11 figure 1.1 how to read the product part no., memory capacity, and package type: g item added 12 figure 1.2 block diagram, changed 13 table 1.8 pin functions: power supply and on-chip emulator, changed 13 table 1.8 pin functions: multiplexed bus, added 18 figure 1.4 pin assignments of the 100-pin lqfp, changed 21 figure 1.7 pin assignments of the 48-pin lqfp, added 23 table 1.9 list of pins and pin func tions (100-pin tflga): pin no. g4, changed 25 table 1.10 list of pins and pin func tions (100-pin lqfp): pin no. 21, changed 28 table 1.11 list of pins and pin func tions (80-pin lqfp): pin no. 19, changed 30 table 1.12 list of pins and pin func tions (64-pin lqfp): pin no. 15, changed 3. address space 37 figure 3.1 memory map in each operating mode: note 2, changed 4. i/o registers 41 to 63 table 4.1 list of i/o registers (address order): number of access, changed voltage regulator control register, timeout internal counter l, timeout internal counter u, and pll power control register, added 63 table 4.1 list of i/o registers (address order): notes 1 and 2, added ? table 4.1 list of i/o registers (address order): loco wait control register 2 (locowtcr2), deleted 5. electrical characteristics 64 to 152 description added 1.30 jan 22, 2013 features 1 on-chip flash memory for code, no wait states, on-chip sram, no wait states, real-time clock, up to 15 communications channels, up to 20 extended-function timers, changed 1.overview 2 to 6 table 1.1 outline of specifications, changed 7 table 1.2 comparison of functi ons for different packages, changed 9 table 1.4 list of products chip version b: d version (ta = -40 to +85c), changed 10 table 1.5 list of products chip version b: g version (ta = -40 to +105c), changed revision history
r01ds0041ej0150 rev.1.50 page 220 of 221 oct 18, 2013 rx210 group revision history 1.30 jan 22, 2013 11 table 1.6 list of products chip version c: d version (ta = -40 to +85c), table 1.7 list of products chip version c: g version (ta = -40 to +105c), changed 12 figure 1.1 how to read the product part no., memory capacity, and package type, changed 13 figure 1.2 block diagram, changed 14 to 17 table 1.8 pin functions, changed 18 figure 1.3 pin assignments of the 145-pin tflga (upper perspective view), added 19 figure 1.4 pin assignments of the 144-pin lqfp, added 25 to 28 table 1.9 list of pins a nd pin functions (145-pin tflga), changed 29 to 32 table 1.10 list of pins and pin functions (144-pin lqfp), changed 3. address space 48 figure 3.1 memory map in each operating mode, changed 4. i/o registers 52 to 81 table 4.1 list of i/o registers (address order, changed 5. electrical characteristics 83 table 5.2 dc characteristics (1), table 5.3 dc characteristics (2), changed 84 to 122 table 5.6 dc characteristics (5) to table 5.20 dc characteristics (19), changed figure 5.1 voltage dependency in high-speed .... for chip version a to figure 5.34 temperature dependency in .... and 100 to 145 pins, changed 158 table 5.55 timing of on-chip peripheral modules (1), changed 159 [512 kbytes or less of flash memory and 48 to 100 pins] table 5.56 timing of on-chip peripheral modules (2), added 160, 161 [768 kbytes/1 mbyte of flash memory or 145/145 pins] table 5.57 timing of on-chip peripheral modules (3), added 162 table 5.58 timing of on-chip peripheral modules (4), changed 165 figure 5.75 mtu/tpu input/output timing, figure 5.76 mtu/tpu clock input timing, changed 166 figure 5.79 sck clock input timing, figure 5.80 sci input/output timing: clock synchronous mode, changed 167 figure 5.82 rspi clock timing and simple spi clock timing, changed 168 figure 5.83 rspi timing (master, cpha = 0) .... and simple spi timing (master, ckph = 1), figure 5.84 rspi timing (master, cpha = 0) (b it rate: pclkb set to divided by 2), changed 169 figure 5.85 rspi timing (master, cpha = 1) .... and simple spi timing (master, ckph = 0), figure 5.86 rspi timing (master, cpha = 1) (b it rate: pclkb set to divided by 2), changed 170 figure 5.87 rspi timing (slave, cpha = 0) and simple spi timing (slave, ckph = 1), figure 5.88 rspi timing (slave, cpha = 1) and simple spi timing (slave, ckph = 0), changed 173 table 5.64 a/d conversion characteristics (2), changed 175 figure 5.91 illustration of a/d converter characteristic terms, absolute accuracy, changed 184 table 5.74 rom (flash memory for code storage) characteristics (1), changed 189 table 5.80 e2 dataflash characteristics (1), table 5.81 e2 dataflash characteristics (2), changed appendix 1. package dimensions 195 figure a 145-pin tflga (ptlg0145ka-a), added 196 figure b 144-pin lqfp (plqp0144ka-a), added 1.40 feb 19, 2013 1. overview 2 to 6 table 1.1 outline of specifications, changed note 2, added 9 table 1.4 list of products chip version b: d version (ta = -40 to +85c), changed 10 table 1.5 list of products chip version b: g version (ta = -40 to +105c), changed note, added 11 table 1.6 list of products chip version c: d version (ta = -40 to +85c): note 1, table 1.7 list of products chip version c: g version (ta = -40 to +105c): note 1 deleted, note added 12 figure 1.1 how to read the product part no., memory capacity, and package type, changed 4. i/o registers 58 table 5.1 list of i/o registers (address order), changed 5. electrical characteristics 83 table 5.4 dc characteristics (3), changed 88 table 5.8 dc characteristics (7), changed rev. date description page summary
r01ds0041ej0150 rev.1.50 page 221 of 221 oct 18, 2013 rx210 group revision history 1.40 feb 19, 2013 96 table 5.11 dc characteristics (10), changed 105 table 5.14 dc characteristics (13), changed 114 table 5.17 dc characteristics (16), changed 115 figure 5.31 voltage dependency in software standby mode (softcut[2:0] bits = 110b) (reference data) for chip version b with 768 kb ytes/1 mbyte of flash memory and 100 to 145 pins, changed 116 figure 5.32 temperature dependency in software standby mode (softcut[2:0] bits = 110b) (reference data) for chip version b with 768 kb ytes/1 mbyte of flash memory and 100 to 145 pins, changed 118 table 5.18 dc characteristics (17), changed 119, 120 table 5.19 dc char acteristics (18), changed 121 to 123 figure 5.35 voltage dependency in high-speed o perating mode (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins to figure 5.39 voltage dependency in low-speed operating mode 2 (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins, added 124 table 5.20 dc characteristics (19), changed 125 to 127 figure 5.40 voltage dependency in software standby mode (softcut[2:0] bits = 110b) (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins to figure 5.43 temperature dependency in deep software standby mode (deepcut1 bit = 1) (reference data) for chip version b with 512 kbytes or less of flash memory and 144 and 145 pins, added 128 table 5.22 dc characteristics (21), changed, note 2 added 144 table 5.44 clock timing: note 5, changed 154 table 5.49 bus timing (1), table 5.50 bus timing (2), changed 155 table 5.51 bus timing (3), changed 160 table 5.52 bus timing (multiplexed bus) (1), t able 5.53 bus timing (mul tiplexed bus) (2), changed 161 table 5.54 bus timing (multiplexed bus) (3), changed 164 table 5.56 timing of on-chip peripheral modules (2), changed 166 table 5.57 timing of on-chip peripheral modules (3), changed 177 table 5.61 a/d conversion characteristics (1), note 3, deleted figure 5.99 avcc to avrefh voltage range, added 179 table 5.64 a/d conversion characteristics (2), note 3, table 5.65 a/d conversion characteristics (3), note 3, deleted 186 table 5.72 power-on reset circuit and voltage detection circuit charac teristics (2), changed 1.50 oct 18, 2013 all 69-pin wlbga package products, added features 1 swbg0069la-a 3.91 4.26mm, 0.40-mm pitch, applications, added 1. overview 2 1.1 outline of specifications, changed 2 to 6 table 1.1 outline of specifications, note 2, changed 7 table 1.2 comparison of functi ons for different packages, changed 8 table 1.3 list of products chip version a: d version (ta = -40 to +85c), changed, note, added 9 table 1.4 list of products chip version b: d version (ta = -40 to +85c), note 1, changed, note added 10 table 1.5 list of products chip version b: g version (ta = -40 to +105c), note, changed, note 1, deleted 11 table 1.6 list of products chip version c: d version (ta = -40 to +85c), table 1.7 list of products chip version c: g version (ta = -40 to +105c), note, changed 12 figure 1.1 how to read the product part no., memory capacity, and package type, changed 23 figure 1.8 pin assignments of the 69-pin wlbga, added 43, 44 table 1.14 list of pins and pin functions (69-pin wlbga), added 5. electrical characteristics 134 table 5.21 dc characteristics (20) note, added 149, 150 table 5.44 clock timing note 6, note 7, added 183 table 5.61 a/d conversion characterist ics (1) note, changed, note 4, deleted 184 table 5.62 channel classification for a/d converter, changed 185 table 5.64 a/d conversion characteristics (2) note, changed appendix 1. package dimensions 211 figure e 69-pin wlbga (swbg0069la-a), added rev. date description page summary
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu pr oducts from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromag netic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal be come possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applie d to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset pr ocess is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provid ed for the possible future expansi on of functions. do not access these addresses; the correct operation of ls i is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program ex ecution, wait until the target clock signal has stabilized. ? when the clock signal is gene rated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only re leased after full stabilization of the clock signal. moreover, when switching to a clock signal produc ed with an external resonator (or by an external oscillator) while program ex ecution is in progress, wait until t he target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of an mpu or mcu in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, ope rating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system-evaluation test for the given product.
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. htt p ://www.renesas.co m refer to "htt p ://www.renesas.com/" for the latest and detailed information . r e n esas el ec tr o ni cs am e ri ca in c . 2880 scott boulevard santa clara , ca 95050-2554 , u.s.a . tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics mala y sia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petalin g jaya, selan g or darul ehsan, malaysi a tel: +60-3-7955-9390 , fax: +60-3-7955-951 0 renesas electronics korea co. , ltd . 11f., samik lavied' or bld g ., 720-2 yeoksam-don g , kan g nam-ku, seoul 135-080, korea tel: +82-2-558-3737 , fax: +82-2-558-514 1 s ale s o ffi c e s ? 2013 renesas electronics corporation. all ri g hts reserved . colo p hon 2.2

▲Up To Search▲

Price & Availability of RX210-15

	To Download RX210-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .